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PDF 3NK80Z Data sheet ( Hoja de datos )

Número de pieza 3NK80Z
Descripción N-CHANNEL Power MOSFET
Fabricantes STMicroelectronics 
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No Preview Available ! 3NK80Z Hoja de datos, Descripción, Manual

STD3NK80Z, STD3NK80Z-1
STF3NK80Z, STP3NK80Z
N-channel 800 V, 3.8 , 2.5 A, TO-220, TO-220FP, DPAK, IPAK
Zener-protected SuperMESH™ Power MOSFET
Features
Type
STP3NK80Z
STF3NK80Z
STD3NK80Z
STD3NK80Z-1
VDSS
(@Tjmax)
800 V
800 V
800 V
800 V
RDS(on)
< 4.5
< 4.5
< 4.5
< 4.5
ID
2.5 A
2.5 A
2.5 A
2.5 A
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatability
Application
Switching applications
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Table 1. Device summary
Order codes
STP3NK80Z
STF3NK80Z
STD3NK80ZT4
STD3NK80Z-1
Marking
P3NK80Z
F3NK80Z
D3NK80Z
D3NK80Z
TO-220
3
2
TO-220FP1
3
1
DPAK
IPAK
3
2
1
Figure 1. Internal schematic diagram
D(2)
G(1)
S(3)
AM01476v1
Package
TO-220
TO-220FP
DPAK
IPAK
Packaging
Tube
Tube
Tape and reel
Tube
September 2009
Doc ID 9565 Rev 6
1/18
www.st.com
18

1 page




3NK80Z pdf
STD3NK80Z, STD3NK80Z-1, STF3NK80Z, STP3NK80Z
2 Electrical characteristics
Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 5.
Symbol
On/off states
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1 mA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = max rating,
VDS = max rating,
Tc = 125 °C
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VGS = 0)
VGS = ± 20 V
Gate threshold voltage
VDS = VGS, ID = 50 µA
Static drain-source on
resistance
VGS = 10 V, ID = 1.25 A
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
3.8 4.5
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance VDS =15 V, ID = 1.25 A
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz,
VGS=0
- 2.1 -
485
- 57 -
11
S
pF
pF
pF
Coss
(2)
eq.
Equivalent output
capacitance
VGS=0, VDS =0 to 640 V
- 22 - pF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Off-voltage rise time
Fall time
VDD=400 V, ID= 1.25 A,
RG= 4.7 Ω, VGS=10 V
(see Figure 19)
17 ns
27 ns
--
36 ns
40 ns
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=640 V, ID = 2.5 A
VGS =10 V
19
- 3.2 -
10.8
nC
nC
nC
1. Pulsed: pulse duration=300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Doc ID 9565 Rev 6
5/18

5 Page





3NK80Z arduino
STD3NK80Z, STD3NK80Z-1, STF3NK80Z, STP3NK80Z
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 9565 Rev 6
11/18

11 Page







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