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Número de pieza | C8051F546 | |
Descripción | Mixed Signal ISP Flash MCU Family | |
Fabricantes | Silicon Laboratories | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de C8051F546 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! Analog Peripherals
- 12-Bit ADC
• Up to 200 ksps
• Up to 25 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Two Comparators
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz;
Typical stop mode current: 1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F54x
Mixed Signal ISP Flash MCU Family
Memory
- 1280 bytes internal data RAM (256 + 1024 XRAM)
- 16 or 8 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 25 or 18 Port I/O; All 5 V tolerant
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy master LIN
operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 32-Pin QFP/QFN (C8051F540/1/4/5)
- 24-Pin QFN (C8051F542/3/6/7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
TEMP
SENSOR
X ADC
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
LIN
Ports 0-3
Crossbar
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
1 kB XRAM
POR WDT
Rev. 1.1 4/11
Copyright © 2011 by Silicon Laboratories
C8051F540/1/2/3/4/5/6/7
1 page C8051F54x
22.1. Signal Descriptions........................................................................................ 215
22.2. SPI0 Master Mode Operation ........................................................................ 216
22.3. SPI0 Slave Mode Operation .......................................................................... 218
22.4. SPI0 Interrupt Sources .................................................................................. 218
22.5. Serial Clock Phase and Polarity .................................................................... 219
22.6. SPI Special Function Registers ..................................................................... 220
23. Timers ................................................................................................................... 227
23.1. Timer 0 and Timer 1 ...................................................................................... 229
23.2. Timer 2 .......................................................................................................... 237
23.3. Timer 3 .......................................................................................................... 243
24. Programmable Counter Array............................................................................. 249
24.1. PCA Counter/Timer ....................................................................................... 250
24.2. PCA0 Interrupt Sources................................................................................. 251
24.3. Capture/Compare Modules ........................................................................... 252
24.4. Watchdog Timer Mode .................................................................................. 260
24.5. Register Descriptions for PCA0..................................................................... 263
25. C2 Interface .......................................................................................................... 269
25.1. C2 Interface Registers................................................................................... 269
25.2. C2 Pin Sharing .............................................................................................. 272
Rev. 1.1
5
5 Page C8051F54x
SFR Definition 16.1. VDM0CN: VDD Monitor Control ................................................ 132
SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 134
SFR Definition 17.1. CLKSEL: Clock Select ............................................................... 136
SFR Definition 17.2. OSCICN: Internal Oscillator Control .......................................... 138
SFR Definition 17.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 139
SFR Definition 17.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 139
SFR Definition 17.5. CLKMUL: Clock Multiplier .......................................................... 141
SFR Definition 17.6. OSCXCN: External Oscillator Control ........................................ 143
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 .......................................... 154
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 .......................................... 155
SFR Definition 18.3. XBR2: Port I/O Crossbar Register 1 .......................................... 156
SFR Definition 18.4. P0MASK: Port 0 Mask Register ................................................. 157
SFR Definition 18.5. P0MAT: Port 0 Match Register .................................................. 157
SFR Definition 18.6. P1MASK: Port 1 Mask Register ................................................. 158
SFR Definition 18.7. P1MAT: Port 1 Match Register .................................................. 158
SFR Definition 18.8. P2MASK: Port 2 Mask Register ................................................. 159
SFR Definition 18.9. P2MAT: Port 2 Match Register .................................................. 159
SFR Definition 18.10. P3MASK: Port 3 Mask Register ............................................... 160
SFR Definition 18.11. P3MAT: Port 3 Match Register ................................................ 160
SFR Definition 18.12. P0: Port 0 ................................................................................. 161
SFR Definition 18.13. P0MDIN: Port 0 Input Mode ..................................................... 162
SFR Definition 18.14. P0MDOUT: Port 0 Output Mode .............................................. 162
SFR Definition 18.15. P0SKIP: Port 0 Skip ................................................................. 163
SFR Definition 18.16. P1: Port 1 ................................................................................. 163
SFR Definition 18.17. P1MDIN: Port 1 Input Mode ..................................................... 164
SFR Definition 18.18. P1MDOUT: Port 1 Output Mode .............................................. 164
SFR Definition 18.19. P1SKIP: Port 1 Skip ................................................................. 165
SFR Definition 18.20. P2: Port 2 ................................................................................. 165
SFR Definition 18.21. P2MDIN: Port 2 Input Mode ..................................................... 166
SFR Definition 18.22. P2MDOUT: Port 2 Output Mode .............................................. 166
SFR Definition 18.23. P2SKIP: Port 2 Skip ................................................................. 167
SFR Definition 18.24. P3: Port 3 ................................................................................. 167
SFR Definition 18.25. P3MDIN: Port 3 Input Mode ..................................................... 168
SFR Definition 18.26. P3MDOUT: Port 3 Output Mode .............................................. 168
SFR Definition 18.27. P3SKIP: Port 3Skip .................................................................. 169
SFR Definition 19.1. LIN0ADR: LIN0 Indirect Address Register ................................. 177
SFR Definition 19.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 177
SFR Definition 19.3. LIN0CF: LIN0 Control Mode Register ........................................ 178
SFR Definition 20.1. SMB0CF: SMBus Clock/Configuration ...................................... 193
SFR Definition 20.2. SMB0CN: SMBus Control .......................................................... 195
SFR Definition 20.3. SMB0DAT: SMBus Data ............................................................ 197
SFR Definition 21.1. SCON0: Serial Port 0 Control .................................................... 210
SFR Definition 21.2. SMOD0: Serial Port 0 Control .................................................... 211
SFR Definition 21.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 212
SFR Definition 21.4. SBCON0: UART0 Baud Rate Generator Control ...................... 212
11 Rev. 1.1
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet C8051F546.PDF ] |
Número de pieza | Descripción | Fabricantes |
C8051F540 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F541 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F542 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F543 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
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