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CAT24WC01ZE-TE13C Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24WC01ZE-TE13C
Beschreibung 1K/2K/4K/8K/16K-Bit Serial E2PROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 9 Seiten
CAT24WC01ZE-TE13C Datasheet, Funktion
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial E2PROM
FEATURES
s 400 KHZ I2C Bus Compatible*
s 1.8 to 6.0Volt Operation
s Low Power CMOS Technology
s Write Protect Feature
— Entire Array Protected When WP at VIH
s Page Write Buffer
DESCRIPTION
s Self-Timed Write Cycle with Auto-Clear
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-pin DIP, 8-pin SOIC or 8 pin TSSOP
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-
bit Serial CMOS E2PROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The the CAT24WC01/02/04/
08/16 feature a 16-byte page write buffer. The device
operates via the I2C bus serial interface, has a special
write protection feature, and is available in 8-pin DIP, 8-
pin SOIC or 8-pin TSSOP.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
5020 FHD F01
TSSOP Package (U)
(* Available for 24WC01 and 24WC02 only)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SDA
START/STOP
LOGIC
XDEC
E2PROM
CONTROL
WP LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WCXX F03
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25051-00 3/98 S-1






CAT24WC01ZE-TE13C Datasheet, Funktion
CAT24WC01/02/04/08/16
Figure 5. Slave Address Bits
24WC01/02 1 0 1 0 A2 A1 A0 R/W
24WC04 1 0 1 0 A2 A1 a8 R/W
24WC08 1 0 1 0 A2 a9 a8 R/W
24WC16 1 0 1 0 a10 a9 a8 R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
line) when its address matches the transmitted slave
address. The CAT24WC01/02/04/08/16 then performs
a Read or Write operation depending on the state of the
R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC01/02/04/08/16 responds with an ac-
knowledge after receiving a START condition and its
slave address. If the device has been selected along
with a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT24WC01/02/04/08/16 is in a READ mode
it transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC01/02/04/08/16 will
continue to transmit data. If no acknowledge is sent by
the Master, the device terminates data transmission and
waits for a STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC01/02/04/08/16. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC01/02/04/08/16 ac-
knowledge once more and the Master generates the
STOP condition, at which time the device begins its
internal programming cycle to nonvolatile memory. While
this internal cycle is in progress, the device will not
respond to any request from the Master device.
Page Write
The CAT24WC01/02/04/08/16 writes up to 16 bytes of
data in a single write cycle, using the Page Write
operation. The Page Write operation is initiated in the
same manner as counter will ‘wrap around’ to address
Doc. No. 25051-00 3/98 S-1
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