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PDF ADG823 Data sheet ( Hoja de datos )
| Número de pieza | ADG823 | |
| Descripción | Dual SPST Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
0.8 ⍀ Max On Resistance @125؇C
0.28 ⍀ Max On Resistance Flatness @125؇C
1.8 V to 5.5 V Single Supply
200 mA Current Carrying Capability
Automotive Temperature Range: –40؇C to +125؇C
Rail-to-Rail Operation
8-Lead MSOP Package
33 ns Switching Times
Typical Power Consumption (<0.01 W)
TTL/CMOS Compatible Inputs
Pin Compatible with ADG721/722/723
APPLICATIONS
Power Routing
Battery-Powered Systems
Communication Systems
Data Acquisition Systems
Audio and Video Signal Routing
Cellular Phones
Modems
PCMCIA Cards
Hard Drives
Relay Replacement
<1 ΩCMOS 1.8 V to 5.5 V,
Dual SPST Switches
ADG821/ADG822/ADG823
FUNCTIONAL BLOCK DIAGRAM
ADG821
ADG822
S1 S1
IN1 IN1
D1 D1
D2 D2
IN2 IN2
S2 S2
ADG823
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC “0”
INPUT
GENERAL DESCRIPTION
The ADG821, ADG822, and ADG823 are monolithic CMOS
SPST (single pole, single throw) switches. These switches are
designed on an advanced submicron process that provides low
power dissipation, yet gives high switching speed, low on
resistance, and low leakage currents.
The ADG821, ADG822, and ADG823 are designed to operate
from a single 1.8 V to 5.5 V supply, making them ideal for use
in battery-powered instruments.
Each switch of the ADG821/ADG822/ADG823 conducts equally
well in both directions when on. The ADG821, ADG822, and
ADG823 contain two independent SPST switches. The ADG821
and ADG822 differ only in that both switches are normally open
and normally closed, respectively. In the ADG823, Switch 1 is
normally open and Switch 2 is normally closed. The ADG823
exhibits break-before-make switching action.
The ADG821, ADG822, and ADG823 are available in an 8-lead
MSOP package.
PRODUCT HIGHLIGHTS
1. Very Low On Resistance (0.5 Ω typ)
2. On Resistance Flatness (RFLAT(ON)) (0.15 Ω typ)
3. Automotive Temperature Range –40°C to +125°C
4. 200 mA Current Carrying Capability
5. Low Power Dissipation. CMOS construction ensures low
power dissipation.
6. 8-Lead MSOP Package
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
PIN CONFIGURATION
8-Lead MSOP
(RM-8)
ADG821/ADG822/ADG823
S1 1 TOP VIEW 8 VDD
D1 2 (Not to Scale) 7 IN1
IN2 3
GND 4
ADG821/
ADG822/
ADG823
6 D2
5 S2
VDD
GND
IDD
S
D
IN
RON
∆RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
VINL
VINH
IINL (IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
tON
tOFF
tBBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
On Response
Insertion Loss
TERMINOLOGY
Most Positive Power Supply Potential
Ground (0 V) Reference
Positive Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic Resistance between D and S
On Resistance Match between any Two Channels (i.e., RON max – RON min)
Flatness is defined as the difference between the maximum and minimum value of on resistance as
measured over the specified analog signal range.
Source Leakage Current with the Switch OFF
Drain Leakage Current with the Switch OFF
Channel Leakage Current with the Switch ON
Analog Voltage on Terminals D and S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
OFF Switch Source Capacitance
OFF Switch Drain Capacitance
ON Switch Capacitance
Delay between Applying the Digital Control Input and the Output Switching ON
Delay between Applying the Digital Control Input and the Output Switching OFF
OFF time or ON time measured between the 90% points of both switches, when switching from one
address state to another.
It is a measure of the glitch impulse transferred from the digital input to the analog output during switching.
It is a measure of unwanted signal that is coupled through from one channel to another as a result
of parasitic capacitance.
A Measure of Unwanted Signal Coupling through an OFF Switch
The Frequency at which the Output Is Attenuated by –3 dBs
The Frequency Response of the ON Switch
The Loss due to the On Resistance of the Switch
REV. 0
–5–
5 Page 
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADG823.PDF ] | |
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