|
|
PDF ADG1219 Data sheet ( Hoja de datos )
| Número de pieza | ADG1219 | |
| Descripción | iCMOS SPDT | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADG1219 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
Low Capacitance, Low Charge Injection,
±15 V/12 V iCMOS SPDT in SOT-23
ADG1219
FEATURES
<0.5 pC charge injection over full signal range
2.5 pF off capacitance
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
8-lead SOT-23 package
FUNCTIONAL BLOCK DIAGRAM
ADG1219
SA
SB D
DECODER
IN EN
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1219 is a monolithic iCMOS® device containing an
SPDT switch. An EN input is used to enable or disable the
device. When disabled, all channels are switched off. When on,
each channel conducts equally well in both directions and has
an input signal range that extends to the supplies. Each switch
exhibits break-before-make switching action.
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor-
mance, dramatically lower power consumption, and reduced
package size.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisi-
tion and sample-and-hold applications, where low glitch and
fast settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
0.5
TA = 25ºC
0.4
0.3
0.2
VDD = +15V
VSS = –15V
0.1
0
–0.1
–0.2
VDD = +12V
VSS = 0V
–0.3
–0.4
–0.5
–15
VDD = +5V
VSS = –5V
–10 –5
0
5 10
INPUT VOLTAGE (V)
Figure 2. Charge Injection vs. Input Voltage
15
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
1 page  
ADG1219
Parameters
POWER REQUIREMENTS
IDD
IDD
ISS
VDD/VSS
25°C
B Version1
−40°C to +85°C −40°C to +125°C
0.001
140
0.001
1.0
190
1.0
±5/±16.5
1 Temperature range for B version is −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Unit
μA typ
μA max
μA typ
μA max
μA typ
μA max
V
min/max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V or VDD
|VDD | = |VSS|
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
25°C
B Version1
−40°C to +85°C −40°C to +125°C
300
475 567
4.5
16 26
60
0 V to VDD
625
27
±0.006
±0.1
±0.006
±0.1
±0.02
±0.2
±0.6
±0.6
±0.6
±1
±1
±1
0.001
3
2.0
0.8
±0.1
195
250 300
120
150 190
145
185 220
70
−0.8
80
340
210
255
10
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
80
dB typ
−3 dB Bandwidth
400 MHz typ
Rev. A | Page 4 of 16
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V or 10 V; see Figure 25
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 28
5 Page 
ADG1219
0
–10
VDD = 15V
VSS = –15V
–20 TA = 25ºC
–30
–40
–50
–60
–70
–80
–90
–100
–110
10k
100k
1M 10M
FREQUENCY (Hz)
100M
Figure 16. Crosstalk vs. Frequency
0
VDD = 15V
–2
VSS = –15V
TA = 25ºC
–4
–6
–8
–10
–12
–14
10k
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 17. On Response vs. Frequency
10.00
LOAD = 10kΩ
TA = 25°C
1G
1G
1.00
0.10
VDD = 5V, VSS = –5V, VS = 3.5V rms
VDD = 15V, VSS = –15V, VS = 5V rms
0.01
10
100 1k 10k
FREQUENCY (Hz)
Figure 18. THD + N vs. Frequency
100k
8
7
SOURCE/DRAIN ON
6
5
DRAIN OFF
4
3 SOURCE OFF
2
VDD = 15V
1 VSS = –15V
TA = 25ºC
0
–15 –10
–5
0
5 10 15
SOURCE VOLTAGE (V)
Figure 19. Capacitance vs. Source Voltage for Dual Supply
9
8
7 SOURCE/DRAIN ON
6
5 DRAIN OFF
4
3 SOURCE OFF
2
VDD = 12V
1 VSS = 0V
TA = 25ºC
0
0 2 4 6 8 10 12
SOURCE VOLTAGE (V)
Figure 20. Capacitance vs. Source Voltage for Single Supply
10
9
8 SOURCE/DRAIN ON
7
6
DRAIN OFF
5
4
3 SOURCE OFF
2 VDD = 5V
1 VSS = –5V
TA = 25ºC
0
–5 –3
–1 1
SOURCE VOLTAGE (V)
3
5
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Rev. A | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADG1219.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADG1211 | (ADG1211 - ADG1213) Quad SPST Switches | Analog Devices |
| ADG1212 | (ADG1211 - ADG1213) Quad SPST Switches | Analog Devices |
| ADG1212-EP | iCMOS Quad SPST Switches | Analog Devices |
| ADG1213 | (ADG1211 - ADG1213) Quad SPST Switches | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |