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ADG1439 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG1439
Beschreibung iCMOS Multiplexers/Matrix Switches
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADG1439 Datasheet, Funktion
Data Sheet
Serially Controlled, ±15 V/+12 V/±5 V, 8-Channel/
4-Channel, iCMOS Multiplexers/Matrix Switches
ADG1438/ADG1439
FEATURES
Serial interface up to 50 MHz
SDO daisy-chaining option
9.5 Ω on resistance at 25°C
1.6 Ω on-resistance flatness
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Rail-to-rail operation
20-lead TSSOP and 20-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
GENERAL DESCRIPTION
The ADG1438 and ADG1439 are CMOS analog matrix switches
with a serially controlled 3-wire interface. The ADG1438 is an
8-channel matrix switch, and the ADG1439 is a dual 4-channel
matrix switch.
The ADG1438/ADG1439 use a versatile 3-wire serial interface
that operates at clock rates of up to 50 MHz and is compatible
with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The output of the shift register, SDO, enables a number
of the ADG1438/ADG1439 devices to be daisy-chained. On
power-up, the internal shift register contains all zeros, and all
switches are in the off state.
Each switch conducts equally well in both directions when on,
making these devices suitable for both multiplexing and
demultiplexing applications. Because each switch is turned on
or off by a separate bit, these devices can also be configured as a
type of switch array, where any, all, or none of the eight switches
can be closed at any time. The input signal range extends to the
supply rails. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and
gain switching applications where low distortion is critical.
iCMOS® construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAMS
ADG1438
S1
D
S8
INPUT SHIFT
REGISTER
SDO
SCLK SYNC DIN RESET
Figure 1.
ADG1439
S1A
S4A
DA
S1B
DB
S4B
INPUT SHIFT
REGISTER
SDO
SCLK SYNC DIN RESET
Figure 2.
PRODUCT HIGHLIGHTS
1. 50 MHz serial interface.
2. 9.5 Ω on resistance.
3. 1.6 Ω on-resistance flatness.
4. 3 V logic-compatible digital input, VINH = 2.0 V, VINL = 0.8 V.
Table 1. Related Devices
Device No.
ADG1408/ADG1409
Description
Low on resistance, parallel
interface, 4-/8-channel ±15 V
multiplexers
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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ADG1439 Datasheet, Funktion
ADG1438/ADG1439
Parameter
Insertion Loss
CS (Off )
CD (Off )
ADG1438
ADG1439
CD, CS (On)
ADG1438
ADG1439
POWER REQUIREMENTS
IDD
+25°C
1.3
14
−40°C to
+85°C
86
42
295
145
0.001
IL Inactive
0.3
IL Active – 30 MHz
IL Active – 50 MHz
ISS
0.26
0.42
0.001
0.3
0.5
VDD
1 Guaranteed by design, not subject to production test.
−40°C to
+125°C
1
1
0.35
0.55
1
5/16.5
Data Sheet
Unit
dB typ
pF typ
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35.
f = 1 MHz.
pF typ
pF typ
f = 1 MHz.
f = 1 MHz.
pF typ
pF typ
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/V max
f = 1 MHz.
f = 1 MHz.
VDD = 13.2 V.
Digital inputs = 0 V or VL.
Digital inputs = 0 V or VL.
Digital inputs toggle between 0 V and VL.
Digital inputs toggle between 0 V and VL.
Digital inputs = 0 V or VL.
Rev. B | Page 6 of 20

6 Page









ADG1439 pdf, datenblatt
ADG1438/ADG1439
Data Sheet
SCLK 1
20 SYNC
VDD 2
DIN 3
GND 4
NIC 5
S1A 6
19 VL
18 SDO
ADG1439
TOP VIEW 17 RESET
(Not to Scale) 16 VSS
15 S1B
S2A 7
14 S2B
S3A 8
13 S3B
S4A 9
12 S4B
DA 10
11 DB
NIC = NO INTERNAL CONNECTION
Figure 7. ADG1439 Pin Configuration (TSSOP)
DIN 1
GND 2
S1A 3
S2A 4
S3A 5
ADG1439
TOP VIEW
(Not to Scale)
15 RESET
14 VSS
13 S1B
12 S2B
11 S3B
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.
Figure 8. ADG1439 Pin Configuration (LFCSP)
Table 11. ADG1439 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
2 20 VDD
3 1 DIN
Most Positive Power Supply Potential.
Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
4 2 GND
Ground (0 V) Reference.
5 8 NIC
No Internal Connection.
6 3 S1A
Source Terminal 1A. Can be an input or an output.
7 4 S2A
Source Terminal 2A. Can be an input or an output.
8 5 S3A
Source Terminal 3A. Can be an input or an output.
9 6 S4A
Source Terminal 4A. Can be an input or an output.
10 7
DA
Drain Terminal A. Can be an input or an output.
11 9
DB
Drain Terminal B. Can be an input or an output.
12 10 S4B
Source Terminal 4B. Can be an input or an output.
13 11 S3B
Source Terminal 3B. Can be an input or an output.
14 12 S2B
Source Terminal 2B. Can be an input or an output.
15 13 S1B
Source Terminal 1B. Can be an input or an output.
16 14 VSS
Most Negative Power Supply Potential. In single-supply applications, it can be connected
to ground.
17 15 RESET
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.
18 16 SDO
19 17 VL
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back
the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of
SCLK and is valid on the falling edge of the clock. This is an open-drain output that should be pulled to the
VL supply with an external 1 kΩ resistor.
Logic Power Supply Input. Operates from 2.7 V to 5.5 V.
20 18 SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the
falling edges of the following clocks. Taking SYNC high updates the switch condition.
N/A1 0
EPAD
The exposed pad is tied to the substrate, VSS.
1 N/A means not applicable.
Rev. B | Page 12 of 20

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