PDF ADGS5412 Data sheet ( Hoja de datos )

Número de pieza	ADGS5412
Descripción	High Voltage Latch-Up Proof Quad SPST Switch
Fabricantes	Analog Devices
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No Preview Available ! Serially-Controlled, High Voltage Latch-Up Proof Quad SPST Switch Preliminary Technical Data ADGS5412 FEATURES SPI interface with Error Detection Includes CRC, Invalid Read/Write Address and SCLK Count Error detection Supports burst and daisy-chain mode Industry standard SPI modes 0 and 3 interface compatible Latch-up proof Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range APPLICATIONS Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION The ADGS5412 contains four independent single-pole/single- throw (SPST) switches. An SPI interface controls the switches. The SPI interface has robust error detection features. These are CRC error detection, Invalid Read/Write Address detection and SCLK count error detection. It is possible to daisy-chain multiple ADGS5412 devices together. This enables the configuration of multiple device with a minimal amount of digital lines. The ADGS5412 can also operate in burst mode to decrease the time between SPI commands. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. FUNCTIONAL BLOCK DIAGRAMS ADGS5412 S1 D1 S2 D2 S3 D3 S4 D4 SPI INTERFACE SDO SCLK SDI CS RESET/VL Figure 1. PRODUCT HIGHLIGHTS 1. SPI Interface removes the need for parallel conversion, logic traces and reduces GPIO channel count. 2. Daisy chain mode removes additional logic traces when multiple devices are used. 3. CRC error detection, Invalid Read/Write Address and SCLK Count Error detection ensures a robust digital interface. 4. SIL Compatible. 5. Trench isolation analog switch section guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Rev. PrB Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADGS5412 Preliminary Technical Data Parameter POWER REQUIREMENTS IDD IL Inactive IL Active at 50MHz ISS VDD/VSS +25°C 45 TBD TBD TBD 0.001 −40°C to +85°C TBD TBD −40°C to +125°C TBD TBD TBD TBD ±9/±22 Unit µA typ µA max µA typ µA max µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL GND = 0 V 1 Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, VL=2.7V to 5.5V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON +25°C −40°C to +85°C −40°C to +125°C Unit VDD to VSS V 9 Ω typ On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) TBD TBD 0.35 TBD TBD 1.5 TBD TBD ±0.05 TBD TBD TBD Ω max Ω typ Ω max Ω typ Ω max nA typ Drain Off Leakage, ID (Off ) TBD TBD ±0.05 TBD nA max nA typ Channel On Leakage, ID (On), IS (On) TBD TBD ±0.1 TBD nA max nA typ DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON tOFF Charge Injection, QINJ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 310 TBD 2 0.8 1.35 0.8 TBD TBD TBD nA max V min V max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max pC typ Rev. PrB \| Page 4 of 28 Test Conditions/Comments VS = ±15 V, IS = −10 mA; see Figure 26 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −10 mA VS = ±15 V, IS = −10 mA VDD = +22 V, VSS = −22 V VS = ±15 V, VD =  15 V; see Figure 29 VS = ±15 V, VD =  15 V; see Figure 29 VS = VD = ±15 V; see Figure 25 3.3V < VL ≤ 5.5V 2.7V ≤ VL ≤ 3.3V VIN = VGND or VL RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 32 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 5 Page ADGS5412 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 24-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V TBD VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first TBD 278 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% −40°C to +125°C −65°C to +150°C 150°C TBD°C/W 260(+0/−5)°C 1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. Preliminary Technical Data Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Rev. PrB \| Page 10 of 28 11 Page

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