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PDF ADG5234 Data sheet ( Hoja de datos )
| Número de pieza | ADG5234 | |
| Descripción | Triple/Quad SPDT Switches | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Latch-up proof
2.8 pF off source capacitance
9 pF off drain capacitance
0.4 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
Human body model (HBM) ESD rating
8 kV input/output port to supplies
2 kV input/output port to input/output port
8 kV all other pins
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5233 and ADG5234 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double throw (SPDT) switches and four indepen-
dently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG5233 (LFCSP and TSSOP packages) is used to
enable or disable the device. When disabled, all channels are
switched off.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
High Voltage Latch-Up Proof,
Triple/Quad SPDT Switches
ADG5233/ADG5234
FUNCTIONAL BLOCK DIAGRAMS
ADG5233
S1A
D1
S1B
S2B
D2
S2A
S3B
D3
S3A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 1. ADG5233 TSSOP and LFCSP_WQ
ADG5234
S1A
D1
S1B
IN1
S4A
D4
S4B
IN4
IN2
S2B
D2
S2A
IN3
S3B
D3
S3A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 2. ADG5234 TSSOP and LFCSP_WQ
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
2. Ultralow Capacitance and 0.4 pC Charge Injection.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5233/ADG5234 can be operated from dual supplies
up to ±22 V.
4. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5233/ADG5234 can be operated from a single-rail
power supply up to 40 V.
5. 3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
6. No VL Logic Power Supply Required.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADG5233/ADG5234
Parameter
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
25°C
−87
370
−5.6
2.8
9
13
50
70
0.001
−40°C to +85°C
−40°C to +125°C
110
1
±9/±22
Unit
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/V max
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF;
see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
25°C −40°C to +85°C −40°C to +125°C Unit
360
500 610
5.5
20 21
170
280 335
0 V to VDD
700
22
370
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
±0.02
±0.1 ±0.2
±0.02
±0.1
±0.08
±0.2
±0.2
±0.3
±0.4
±0.4
±0.9
nA typ
nA max
nA typ
nA max
nA typ
nA max
0.002
3
2.0 V min
0.8 V max
μA typ
±0.1 μA max
pF typ
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA;
see Figure 28
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 30
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 30
VS = VD = 1 V/10 V; see Figure 26
VIN = VGND or VDD
Rev. D | Page 5 of 22
5 Page 
Data Sheet
ADG5233/ADG5234
IN1 1
20 IN4
S1A 2
19 S4A
D1 3
18 D4
S1B 4 ADG5234 17 S4B
VSS 5 TOP VIEW 16 VDD
GND 6 (Not to Scale) 15 NC
S2B 7
14 S3B
D2 8
13 D3
S2A 9
12 S3A
IN2 10
11 IN3
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 5. ADG5234 TSSOP Pin Configuration
D1 1
S1B 2
VSS 3
GND 4
S2B 5
ADG5234
TOP VIEW
15 D4
14 S4B
13 VDD
12 S3B
11 D3
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 6. ADG5234 LFCSP_WQ Pin Configuration
Table 10. ADG5234 Pin Function Descriptions
Pin No.
TSSOP LFCSP_WQ Mnemonic Description
1 19
IN1 Logic Control Input 1.
2 20
S1A Source Terminal 1A. This pin can be an input or an output.
31
D1 Drain Terminal 1. This pin can be an input or an output.
42
S1B Source Terminal 1B. This pin can be an input or an output.
53
VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to
ground.
64
GND
Ground (0 V) Reference.
75
S2B Source Terminal 2B. This pin can be an input or an output.
86
D2 Drain Terminal 2. This pin can be an input or an output.
97
S2A Source Terminal 2A. This pin can be an input or an output.
10 8
IN2 Logic Control Input 2.
11 9
IN3 Logic Control Input 3.
12 10
S3A Source Terminal 3A. This pin can be an input or an output.
13 11
D3 Drain Terminal 3. This pin can be an input or an output.
14 12
S3B Source Terminal 3B. This pin can be an input or an output.
15 N/A
NC
No Connect. This pin is open.
16 13
VDD Most Positive Power Supply Potential.
17 14
S4B Source Terminal 4B. This pin can be an input or an output.
18 15
D4 Drain Terminal 4. This pin can be an input or an output.
19 16
S4A Source Terminal 4A. This pin can be an input or an output.
20 17
IN4 Logic Control Input 4.
N/A 18
EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx
logic inputs determine the on switches.
N/A 21 EP Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5234 Truth Table
INx
0
1
SxA
Off
On
SxB
On
Off
Rev. D | Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADG5234.PDF ] | |
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