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ADCMP392 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADCMP392
Beschreibung Single/Dual/Quad Comparators
Hersteller Analog Devices
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Gesamt 17 Seiten
ADCMP392 Datasheet, Funktion
Data Sheet
Single/Dual/Quad Comparators
With Known Power-Up State
ADCMP391/ADCMP392/ADCMP393
FEATURES
Single-supply voltage operation: 2.3 V to 5.5 V
Rail-to-rail common-mode input voltage range
Low input offset voltage across VCMR: 1 mV typical
Guarantees comparator output logic low from VCC = 0.9 V to
undervoltage lockout (UVLO)
Operating temperature range: −40°C to +125°C
Package types:
8-lead, narrow body SOIC (ADCMP391/ADCMP392)
14-lead, narrow body SOIC (ADCMP393)
14-lead TSSOP (ADCMP393)
APPLICATIONS
Battery management/monitoring
Power supply detection
Window comparators
Threshold detectors/discriminators
Microprocessor systems
GENERAL DESCRIPTION
The ADCMP391/ADCMP392/ADCMP393 are
single/dual/quad rail-to-rail input, low power comparators ideal
for use in general-purpose applications. These comparators
operate from a single supply voltage of 2.3 V to 5.5 V and draw
a minimal amount of current. The single ADCMP391
consumes only 18.6 µA of supply current. The dual ADCMP392
and the quad ADCMP393 consumes 22.1 µA and 26.8 µA of
supply current, respectively. The low voltage and low current
operation of these devices makes it ideal for battery-powered
systems.
The comparators features a common-mode input voltage range
of 200 mV beyond rails, an offset voltage of 1 mV typical across
the full common-mode range, and a UVLO monitor. In addition,
the design of the comparators allows a defined output state
upon power-up, a logic low output while the supply voltage is
less than the UVLO threshold.
The ADCMP391 and ADCMP392 are available in 8-lead,
narrow body SOIC package while the ADCMP393 is available
in a 14-lead, narrow body SOIC package and a 14-lead TSSOP
package. The comparators are specified to operate over the
−40°C to +125°C extended temperature range.
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADCMP391
IN+
OUT
IN–
GND
Figure 1.
VCC
INA+
INA–
INB+
INB–
ADCMP392
OUTA
OUTB
GND
Figure 2.
VCC
INA+
INA–
INB+
INB–
INC+
INC–
IND+
IND–
ADCMP393
OUTA
OUTB
OUTC
OUTD
GND
Figure 3.
Rev. D
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ADCMP392 Datasheet, Funktion
ADCMP391/ADCMP392/ADCMP393
Data Sheet
OUTB 1
OUTA 2
VCC 3
INA– 4
INA+ 5
INB– 6
INB+ 7
ADCMP393
TOP VIEW
(Not to Scale)
14 OUTC
13 OUTD
12 GND
11 IND+
10 IND–
9 INC+
8 INC–
Figure 6. ADCMP393 SOIC Pin Configuration
Table 6. ADCMP393 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OUTB
Comparator B Output, Open Drain
2
OUTA
Comparator A Output, Open Drain
3 VCC Device Supply Input
4
INA−
Comparator A Inverting Input
5
INA+
Comparator A Noninverting Input
6
INB−
Comparator B Inverting Input
7
INB+
Comparator B Noninverting Input
8
INC−
Comparator C Inverting Input
9
INC+
Comparator C Noninverting Input
10
IND−
Comparator D Inverting Input
11
IND+
Comparator D Noninverting Input
12
GND
Device Ground
13
OUTD
Comparator D Output, Open Drain
14
OUTC
Comparator C Output, Open Drain
OUTB 1
OUTA 2
VCC 3
INA– 4
INA+ 5
INB– 6
INB+ 7
14 OUTC
13 OUTD
ADCMP393
TOP VIEW
(Not to Scale)
12 GND
11 IND+
10 IND–
9 INC+
8 INC–
Figure 7. ADCMP393 TSSOP Pin Configuration
Rev. D | Page 6 of 17

6 Page









ADCMP392 pdf, datenblatt
ADCMP391/ADCMP392/ADCMP393
Data Sheet
WINDOW COMPARATOR FOR NEGATIVE VOLTAGE
MONITORING
Figure 30 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
divider circuit, in this case, VREF.
VREF
RZ
VNH
INA+
INA–
OUTA
RY VREF
VNL
RX
INB+
INB–
OUTB
VM
Figure 30. Negative Undervoltage/Overvoltage Monitoring Configuration
Equation 7, Equation 9, and Equation 10 need some minor
modifications for use with negative voltage monitoring. The
reference voltage, VREF, is added to the overall voltage drop;
therefore, it must be subtracted from VM, VUV, and VOV before
using each of them in Equation 7, Equation 9, and Equation 10.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between VREF and the
negative supply voltage into the high-side voltage, VNH, and the
low-side voltage, VNL. The high-side voltage, VNH, is connected
to INC+, and the low-side voltage, VNL, is connected to IND−.
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, VNH) on the INC+ pin must be
more negative than ground. Calculate the high-side voltage,
VNH, by the following:
( )VNH
= GND =  VREF

VOV

R
RX +
X + RY
RY
+
RZ
 + VOV
(11)
In addition,
( )RX + RY
+ RZ
=
VM VREF
IM
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated by
(12)
( ( ))RZ
= VREF VM VREF
I M VREF VOV
(13)
To trigger an undervoltage condition, the monitored voltage
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, VNL) on the IND− pin
must be more positive than ground. Calculate the low-side
voltage, VNL, by the following:
( )VNL
= GND =  VREF

VUV

RX
RX
+ RY
+ RZ
 + VUV
(14)
Because RZ is already known, RY can be expressed as follows:
(( ))RY
= VREF VM VREF
I M VREF VUV
RZ
(15)
When RY and RZ are known, RX is then calculated by
( )RX
=
VM VREF
IM
RY RZ
(16)
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
The circuit shown in Figure 31 is used to control the power
supply sequencing. The delay is set by the combination of the
pull-up resistor (RPULLUP), the load capacitor (CL), and the
resistor divider network.
VREF/VCC
SEQ
RPULLUP
CL
R5
V4
R4
V3
R3
V2
R2
V1
R1
INA+
INA–
INB+
INB–
INC+
INC–
IND+
IND–
U1
OUTA
OUTB
OUTC
OUTD
Figure 31. Programmable Sequencing Control Circuit
Figure 32 shows a simplified block diagram for the
programmable sequencing control circuit. The application
delays the enable signal, EN, of the external regulators (LDO x)
in a linear order when the open-drain signal (SEQ) changes
from low to high impedance.
The ADCMP391/ADCMP392/ADCMP393 have a defined
output state during startup, which prevents any regulator from
turning on if VCC is still below the UVLO threshold.
3.3V
IN OUT
LDO 1
EN
GND
3.0V
VREF/VCC
t1
SEQ
t2
t3
t4
GND
IN OUT
LDO 2
EN
GND
1.8V
IN OUT
LDO 3
EN
GND
2.5V
IN OUT
LDO 4
EN
GND
1.2V
Figure 32. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
Rev. D | Page 12 of 17

12 Page





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