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PDF ADAU1966A Data sheet ( Hoja de datos )
| Número de pieza | ADAU1966A | |
| Descripción | 24-Bit DAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Channel, High Performance,
192 kHz, 24-Bit DAC
ADAU1966A
FEATURES
GENERAL DESCRIPTION
Differential or single-ended voltage DAC output
The ADAU1966A is a high performance, single-chip digital-to-
114 dB DAC dynamic range, A-weighted, differential
analog converter (DAC) that provides 16 DACs with differential or
−97 dB total harmonic distortion plus noise (THD + N),
single-ended outputs using the Analog Devices, Inc., patented
differential
multibit sigma-delta (Σ-Δ) architecture. A serial peripheral interface
110 dB DAC dynamic range, A-weighted, single-ended
(SPI)/I2C port is included, allowing a microcontroller to adjust
−95 dB THD + N, single-ended
volume and many other parameters. The ADAU1966A operates
2.5 V digital and 3.3 V analog and input/output (I/O) supplies
from 2.5 V digital and 3.3 V analog supplies. A linear regulator
299 mW total quiescent power
is included to generate the digital supply voltage from the analog
Phase-locked loop (PLL) generated or direct master clock
supply voltage. The ADAU1966A is available in an 80-lead LQFP.
Low electromagnetic interference (EMI) design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout ±3°C accuracy
SPI and I2C controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave modes with up to 16-channel input/output
80-lead LQFP package
The ADAU1966A is designed for low EMI. This consideration
is apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock from
an external left-right frame clock (LRCLK), the ADAU1966A
can eliminate the need for a separate high frequency master clock
and can be used with or without a bit clock. The DACs are
designed using the latest Analog Devices continuous time
architectures to further minimize EMI. By using 2.5 V digital
supplies, power consumption is minimized, and the digital
waveforms are a smaller amplitude, further reducing emissions.
Note that throughout this data sheet, multifunction pins, such as
Qualified for automotive applications
SCLK/SCL, are referred to by the entire pin name or by a single
APPLICATIONS
function of the pin, for example, SCLK, when only that function
is relevant.
Automotive audio systems
Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
ANALOG
AUDIO
OUTPUTS
ADAU1966A
DAC
DAC
DAC
DAC
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
PRECISION
VOLTAGE
REFERENCE
SERIAL DATA PORT
SDATA
IN
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
SPI/I2C
CONTROL PORT
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
INTERNAL
TEMP
SENSOR
ANALOG
AUDIO
OUTPUTS
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADAU1966A
Data Sheet
ANALOG PERFORMANCE SPECIFICATIONS: TA = 105°C
Specifications guaranteed at supply voltages of AVDDx = 3.3 V, DVDD = 2.5 V, ambient temperature1 (TA) = 105°C, unless otherwise
noted.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (DNR)
No Filter (RMS)
With A-Weighted Filter (RMS)
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Differential Output
Single-Ended Output
Full-Scale Differential Output Voltage
Full-Scale Single-Ended Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-Emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
Test Conditions/Comments
20 Hz to 20 kHz, −60 dB input
Differential output
Differential output
Single-ended output
Single-ended output
Two channels running −1 dBFS
All channels running −1 dBFS
Two channels running −1 dBFS
All channels running −1 dBFS
TS_REF pin
CM pin
CM pin
VSUPPLY pin
VSENSE pin
Min Typ
Max Unit
106.5
109.5
101.5
104.5
110
113
108
110
dB
dB
dB
dB
−92 −83 dB
−92 −83 dB
−90 −80 dB
−90 −80 dB
2.00 (2.83)
V rms (V p-p)
1.00 (1.41)
V rms (V p-p)
−10 +10 %
−25 −6
+25 mV
−30 +30 ppm/°C
100 dB
0 Degrees
0.375
dB
95.25
dB
±0.6 dB
33 Ω
1.50
1.40 1.50
1.40 1.50
V
1.56 V
1.56 V
3.14 3.3
2.25 2.50
3.46 V
2.55 V
−3
−60
1
0.25
+3
+140
6
°C
°C
°C
Hz
1 Functionally guaranteed at −40°C to +125°C, case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
TRANSCONDUCTANCE
TA = 25°C
TA = 105°C
Min
6.4
5.2
Typ
7 to 10
7.5 to 8.5
Max
14
12
Unit
mmhos
mmhos
Rev. A | Page 4 of 52
5 Page 
ADAU1966A
Data Sheet
Pin No.
20, 29, 41
21, 26, 30, 40
22, 39
23
24
25
27
28
31
32
33
34
35
36
37
38
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Mnemonic1, 2
DVDD
DGND
IOVDD
VSENSE
VDRIVE
VSUPPLY
DBCLK
DLRCLK
SA1
SA2
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
MOSI/ADDR1/SA
MISO/SDA/SA
SCLK/SCL
SS/ADDR0/SA
SA_MODE
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
TS_REF
DAC5P
DAC5N
DAC6P
DAC6N
DAC7P
Type3
PWR
GND
PWR
I
O
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I/O
I
I
I
I
GND
PWR
O
O
O
O
O
O
O
O
PWR
I
I
GND
O
O
O
O
O
O
O
Description
Digital Power, 2.5 V.
Digital Ground.
Power for Digital Input and Output Pins, 3.3 V.
2.5 V Regulator Output, Pass Transistor Collector. Bypass VSENSE with a 10 μF capacitor in parallel
with a 100 nF capacitor.
Pass Transistor Base Driver.
3.3 V Voltage Regulator Input , Pass Transistor Emitter . Bypass VSUPPLY with a 10 μF capacitor in
parallel with a 100 nF capacitor.
Bit Clock for DACs.
Frame Clock for DACs.
Standalone Mode, Time Domain Multiplexed (SA_MODE TDM) State. See the Standalone Mode
section, Table 13, and Table 14, for more information.
Standalone Mode, Time Domain Multiplexed (SA_MODE TDM) State. See the Standalone Mode
section, Table 13, and Table 14, for more information.
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Master Output Slave Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
Master Output Slave Input (SPI)/Control Data Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 13).
Serial Clock Input (SPI)/Control Clock Input (I2C).
Slave Select (SPI) (Active Low)/Address 0 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
Standalone Mode. This pin allows mode control of ADAU1966A using Pin 42, Pin 43, Pin 45,
Pin 31, and Pin 32 (high active). See Table 13 and Table 14 for more information).
Power-Up/Reset (Active Low). See Power-Up and Reset section for more information.
Analog Ground.
Analog Power.
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple Pin 59 with a 470 nF capacitor to AVDD2.
DAC Bias 2. AC couple Pin 60 with a 470 nF capacitor to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass the CM pin with a 10 μF capacitor
in parallel with a 100 nF capacitor to AGND2. This reference can be shut off in the
PLL_CLK_CTRL1 register (Register 0x01) and the pin can be driven with an outside voltage
source.
Voltage Reference Filter Capacitor Connection. Bypass Pin 63 with a 10 μF capacitor in parallel with a
100 nF capacitor to AGND2.
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
DAC7 Positive Output.
Rev. A | Page 10 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADAU1966A.PDF ] | |
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