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AD1941 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1941
Beschreibung SigmaDSP Multichannel 28-Bit Audio Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD1941 Datasheet, Funktion
FEATURES
16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully programmable program RAM for custom
program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter
updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic
parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or
512 × fS clocks
Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio
delay at fs = 48 kHz
Flexible serial data port with I2S-compatible, left-justified,
and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and
5 V systems
Programmable low power mode
Fast start-up and boot time from power-on or reset
48-lead LQFP plastic package
GENERAL DESCRIPTION
The AD1940/AD1941 are a complete 28-bit, single-chip, multi-
channel audio SigmaDSPfor equalization, multiband dynamic
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compen-
sate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940/AD1941 is
comparable to that found in high end studio equipment. Most
of the processing is done in full, 56-bit double-precision mode,
resulting in very good, low level signal performance and the
absence of limit cycles or idle tones. The dynamics processor
uses a sophisticated, multiple-breakpoint algorithm often found
in high end broadcast compressors.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SigmaDSP Multichannel
28-Bit Audio Processor
AD1940/AD1941
APPLICATIONS
Automotive sound systems
Digital televisions
Home theater systems (Dolby digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)
FUNCTIONAL BLOCK DIAGRAM
4
SERIAL DATA/
TDM INPUTS
VOLTAGE
REGULATOR
2
AD1940/AD1941
28 × 28
DSP CORE
2
2
MASTER
CLOCK
INPUT
PLL
4
SPI/I2C I/O
SERIAL
CONTROL
INTERFACE
DATA FORMAT:
5.23 (SINGLE
PRECISION)
10.46 (DOUBLE
PRECISION)
RAM ROM
SERIAL
DATA/
TDM
OUTPUTS
Figure 1.
The AD1940/AD1941 are a fully programmable DSP. Easy to
use software allows the user to graphically configure a custom
signal processing flow using blocks such as biquad filters, dyna-
mics processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1940/AD1941’s digital input and output ports allow a
glueless connection to ADCs and DACs by multiple, 2-channel
serial data streams or TDM data streams. When in TDM mode,
the AD1940/AD1941 can input 8 or 16 channels of serial data,
and can output 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1940
is controlled by a 4-wire SPI® port; the AD1941 is controlled by
a 2-wire I2C® bus. Other than the control interface, the
functions of the two parts are identical.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved.






AD1941 Datasheet, Funktion
AD1940/AD1941
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Min Max
VDD to DGND
–0.3
+3.0
PLL_ VDD to PGND –0.3
+3.0
OD VDD to DGND
–0.3
+6.0
INVDD to DGND
ODVDD
+6.0
Digital Inputs
DGND – 0.3 INVDD + 0.3
Maximum Junction
Temperature
135
Storage Temperature –65
Range
+150
Soldering (10 sec)
300
Unit
V
V
V
V
V
°C
°C
°C
Table 9. Package Characteristics
Parameter
θJA Thermal Resistance (Junction-
to-Ambient)
θJC Thermal Resistance (Junction-
to-Case)
Min Typ Max Unit
72 °C/W
19.5 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 36

6 Page









AD1941 pdf, datenblatt
AD1940/AD1941
PIN FUNCTIONS
Table 10 shows the AD1940/AD1941’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by
writing to Bits 2:0 of the serial input port control register.
SDATA_IN2 and SDATA_IN3 are dual-function pins that can
be set to a variety of standard 2-channel formats or to TDM
mode. Two of these four pins (SDATA_IN2 and SDATA_IN3)
can be used as TDM inputs in either dual-wire 8-channel mode
or single-wire 16-channel mode (TDM_O0 only). In dual-wire
8-channel mode, Channels 0 to 7 are input on SDATA_IN3 and
Channels 8 to 15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0 to 15 are input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0 through
SDATA_IN3 signals. The input port is always in a slave
configuration. These pins also function as frame sync and bit
clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard 2-channel formats. They are grouped into two groups
of four pins (Pins 0 to 3 and Pins 4 to 7); each group can be
independently set to any of the available serial modes, allowing
the AD1940/AD1941 to simultaneously communicate with two
external devices with different serial formats. Two of these eight
pins (SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire 16-
channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0 to 7 are output on SDATA_OUT0 and
Channels 8 to 15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0 through SDATA_OUT3. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4 through SDATA_OUT7. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
MCLK
Master Clock Input. The AD1940/AD1941 uses a PLL to
generate the appropriate internal clock for the DSP core. An
in-depth description of using the PLL is found in the Setting
Master Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
CDATA (AD1940)
Serial Data Input for the SPI Control Port.
COUT (AD1940)
Serial Data Output for the SPI Port. This is used for reading
back registers and memory locations. It is three-stated when an
SPI read is not active.
CCLK (AD1940)
SPI Bit Clock. This clock may either run continuously or be
gated off between SPI transactions.
CLATCH (AD1940)
SPI Latch Signal. This must go low at the beginning of an SPI
transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction.
SCL (AD1941)
I2C Clock. This pin is always an input because the AD1941
cannot act as a master on the I2C bus. The line connected to this
pin should have a 2 kΩ pull-up resistor on it.
SDA (AD1941)
I2C Serial Data. The data line is bidirectional. The line
connected to this pin should have a 2 kΩ pull-up resistor on it.
Rev. B | Page 12 of 36

12 Page





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