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PDF AD1940 Data sheet ( Hoja de datos )
| Número de pieza | AD1940 | |
| Descripción | SigmaDSP Multichannel 28-Bit Audio Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully programmable program RAM for custom
program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter
updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic
parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or
512 × fS clocks
Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio
delay at fs = 48 kHz
Flexible serial data port with I2S-compatible, left-justified,
and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and
5 V systems
Programmable low power mode
Fast start-up and boot time from power-on or reset
48-lead LQFP plastic package
GENERAL DESCRIPTION
The AD1940/AD1941 are a complete 28-bit, single-chip, multi-
channel audio SigmaDSP™ for equalization, multiband dynamic
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compen-
sate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940/AD1941 is
comparable to that found in high end studio equipment. Most
of the processing is done in full, 56-bit double-precision mode,
resulting in very good, low level signal performance and the
absence of limit cycles or idle tones. The dynamics processor
uses a sophisticated, multiple-breakpoint algorithm often found
in high end broadcast compressors.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SigmaDSP Multichannel
28-Bit Audio Processor
AD1940/AD1941
APPLICATIONS
Automotive sound systems
Digital televisions
Home theater systems (Dolby digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)
FUNCTIONAL BLOCK DIAGRAM
4
SERIAL DATA/
TDM INPUTS
VOLTAGE
REGULATOR
2
AD1940/AD1941
28 × 28
DSP CORE
2
2
MASTER
CLOCK
INPUT
PLL
4
SPI/I2C I/O
SERIAL
CONTROL
INTERFACE
DATA FORMAT:
5.23 (SINGLE
PRECISION)
10.46 (DOUBLE
PRECISION)
RAM ROM
SERIAL
DATA/
TDM
OUTPUTS
Figure 1.
The AD1940/AD1941 are a fully programmable DSP. Easy to
use software allows the user to graphically configure a custom
signal processing flow using blocks such as biquad filters, dyna-
mics processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1940/AD1941’s digital input and output ports allow a
glueless connection to ADCs and DACs by multiple, 2-channel
serial data streams or TDM data streams. When in TDM mode,
the AD1940/AD1941 can input 8 or 16 channels of serial data,
and can output 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1940
is controlled by a 4-wire SPI® port; the AD1941 is controlled by
a 2-wire I2C® bus. Other than the control interface, the
functions of the two parts are identical.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113©2004–2010 Analog Devices, Inc. All rights reserved.
1 page  
PLL
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 5.
Parameter
Lock Time
Min
Typ
3
REGULATOR
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 6.
Parameter
VSENSE Output Voltage
Min
2.25
Typ
2.5
TEMPERATURE RANGE
Table 7.
Parameter
Functionality Guaranteed
Min Typ
–40
–40
AD1940/AD1941
Max Unit
20 ms
Max
2.68
Max
+105
+125
Unit
V
Unit
°C Ambient
°C Case
Rev. B | Page 5 of 36
5 Page 
FEATURES
The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double
precision) optimized for audio processing. The parts’ program
RAM can be loaded with a custom program after power-up.
Signal processing parameters are stored in a 1024 location
parameter RAM, which is initialized on power-up by an
internal boot ROM. New values are written to the parameter
RAM using the control port. The values stored in the parameter
RAM control individual signal processing blocks, such as IIR
equali-zation filters, dynamics processors, audio delays, and
mixer levels. A safeload feature allows parameters to be
transparently updated without causing clicks on the output
signals.
The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.
The AD1940/AD1941 contain eight independent data capture
circuits that can be programmed to tap the signal flow of the
processor at any point in the DSP algorithm flow. Six of these
captured signals can be accessed by reading from the data
capture registers through the control port. The remaining two
data capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.
AD1940/AD1941
The AD1940/AD1941 have a sophisticated control port that
supports complete read/write capability of all memory
locations. Five control registers (Core, RAM configuration,
Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are
provided to offer complete control of the chip’s configuration
and serial modes. Handshaking is included for ease of memory
uploads/downloads. The AD1940 is SPI-controlled and the
AD1941 is controlled by an I2C bus.
The AD1940/AD1941 have very flexible serial data
input/output ports that allow glueless interconnection to a
variety of ADCs, DACs, general-purpose DSPs, S/PDIF
receivers and trans-mitters, and sample rate converters. The
AD1940/AD1941 can be configured in I2S, left-justified, right-
justified, or TDM serial port-compatible modes. It can support
16, 20, and 24 bits in all modes. The AD1940/AD1941 accepts
serial audio data in MSB first and twos complement format.
A master clock phase-locked loop (PLL) allows the AD1940/
AD1941 to be clocked from a variety of different clock speeds.
The PLL can accept inputs of 64 × fS, 256 × fS, 384 × fS, or 512 ×
fS to generate the core’s internal master clock.
The AD1940/AD1941 operate from a single 2.5 V power supply.
An on-board voltage regulator can be used to operate the chip
with 3.3 V or 5 V supplies. They are fabricated on a single
monolithic integrated circuit and are housed in 48-lead
LQFP packages for operation over the –40°C to +105°C
temperature range.
SERIAL
DATA/TDM
INPUT
GROUP
PLL MODE
SELECT
MASTER
CLOCK
INPUT
CONTROL PORT
I/O GROUP
ADDRESS SELECT
RESETB
DATA MEMORY
6k × 28
TARGET/SLEW
RAM
2 64 × 28
2
MCLK
PLL
CONTROL
REGISITER
4 SERIAL
CONTROL TRAP REG.
PORT
SAFELOAD
REGISTER
28 × 28
DSP CORE
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
2
2
SERIAL DATA/
TDM OUTPUT
GROUP
PROGRAM
RAM
1536 × 40
PARAMETER
RAM
1024 × 28
COEFFICIENT
ROM
512 × 28
MEMORY CONTROLLERS
VOLTAGE REGULATOR
4
REGULATOR
GROUP
Figure 9. Block Diagram
Rev. B | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1940.PDF ] | |
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