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ADV7281 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7281
Beschreibung 4x Oversampled SDTV Video Decoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7281 Datasheet, Funktion
Data Sheet
10-Bit, 4× Oversampled SDTV Video
Decoder with Differential Inputs
ADV7281
FEATURES
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
Analog video input channels with on-chip antialiasing filter
ADV7281: up to 4 input channels
ADV7281-M: up to 6 input channels
ADV7281-MA: up to 8 input channels
Video input support for CVBS (composite), Y/C (S-Video),
and YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
Short-to-battery (STB) diagnostics on 2 video inputs
(ADV7281 and ADV7281-M only)
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
mini-time base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive
peak white mode
Fast switching capability
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi (Macrovision) copy protection detection
MIPI CSI-2 output interface (ADV7281-M and ADV7281-MA)
8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7281)
Full featured vertical blanking interval (VBI) data slicer
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
APPLICATIONS
Smartphone/multimedia handsets
Automotive infotainment
DVRs for video security
Media players
GENERAL DESCRIPTION
The ADV7281/ADV7281-M/ADV7281-MA are versatile
one-chip, multiformat video decoders. The ADV7281/
ADV7281-M/ADV7281-MA automatically detect standard
analog baseband video signals compatible with worldwide
NTSC, PAL, and SECAM standards in the form of composite,
S-Video, and component video.
The ADV7281 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The ADV7281-M/ADV7281-MA convert the analog video
signals into an 8-bit YCrCb 4:2:2 video data stream that is
output over a mobile industry processor interface (MIPI®)
CSI-2 interface.
The analog video inputs of the ADV7281/ADV7281-M/
ADV7281-MA accept single-ended, pseudo differential, and
fully differential signals. The ADV7281 provides four analog
inputs and two STB diagnostic pins. The ADV7281-M provides
six analog inputs, two STB diagnostic pins, and three general-
purpose outputs. The ADV7281-MA provides eight analog
inputs and three general-purpose outputs.
The ADV7281/ADV7281-M/ADV7281-MA are programmed
via a 2-wire, serial bidirectional port (I2C compatible) and
are fabricated in a 1.8 V CMOS process. The ADV7281/
ADV7281-M/ADV7281-MA are provided in space-saving
LFCSP surface-mount, RoHS-compliant packages. The
ADV7281/ADV7281-M/ADV7281-MA are rated over the
−40°C to +105°C temperature range. This makes the ADV7281/
ADV7281-M/ADV7281-MA ideal for automotive applications.
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADV7281 Datasheet, Funktion
Data Sheet
ADV7281
Parameter
Symbol Test Conditions/Comments Min Typ Max Unit
POWER-DOWN CURRENTS1
Digital I/O Supply Power-Down
Current
IDVDDIO_PD
DVDDIO = 3.3 V, ADV7281-M/
ADV7281-MA
73 μA
DVDDIO = 3.3 V, ADV7281
84 μA
PLL Supply Power-Down Current
IPVDD_PD
46 μA
Analog Supply Power-Down Current IAVDD_PD
0.2 μA
Digital Supply Power-Down Current
IDVDD_PD
420 μA
MIPI Tx Supply Power-Down Current IMVDD_PD ADV7281-M and ADV7281-MA only
4.5
μA
Total Power Dissipation
in Power-Down Mode
1 mW
1 Guaranteed by characterization.
2 Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.
VIDEO SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 2.
Parameter
Symbol Test Conditions/Comments Min Typ Max Unit
NONLINEAR SPECIFICATIONS1
Differential Phase
DP CVBS input, modulated 5-step
0.9
Degrees
Differential Gain
DG CVBS input, modulated 5-step
0.5
%
Luma Nonlinearity
LNL CVBS input, 5-step
2.0 %
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted
SNR
Luma ramp
57.1 dB
Luma flat field
58 dB
Analog Front-End Crosstalk
60 dB
Common-Mode Rejection Ratio2
CMRR
73 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
−5 +5 %
Vertical Lock Range
40 70 Hz
fSC Subcarrier Lock Range
±1.3 kHz
Color Lock-In Time
60 Lines
Synchronization Depth Range
20 200 %
Color Burst Range
5 200 %
Vertical Lock Time
2 Fields
Autodetection Switch Speed3
100 Lines
Fast Switch Speed4
100 ms
LUMA SPECIFICATIONS
CVBS, 1 V input
Luma Brightness Accuracy
1%
Luma Contrast Accuracy
1%
1 These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs.
2 The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3 Autodetection switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to detect which video format is present at its input, for example, PAL I or
NTSC M.
4 Fast switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to switch from one analog input (single-ended or differential) to another, for
example, switching from AIN1 to AIN2.
Rev. B | Page 5 of 32

6 Page









ADV7281 pdf, datenblatt
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADV7281
DGND 1
DVDDIO 2
DVDD 3
DGND 4
P7 5
P6 6
P5 7
P4 8
ADV7281
TOP VIEW
(Not to Scale)
24 AIN3
23 DIAG2
22 DIAG1
21 AVDD
20 VREFN
19 VREFP
18 AIN2
17 AIN1
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 7. Pin Configuration, ADV7281
Table 9. Pin Function Descriptions, ADV7281
Pin No.
Mnemonic Type
Description
1, 4
DGND
Ground
Ground for Digital Supply.
2
3, 13
5 to 12
DVDDIO
DVDD
P7 to P0
Power
Power
Output
Digital I/O Power Supply (1.8 V or 3.3 V).
Digital Power Supply (1.8 V).
Video Pixel Output Ports.
14
XTALP
Output
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281. The crystal used
with the ADV7281 must be a fundamental crystal.
15
XTALN
Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281must be
a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7281, the output of the oscillator is fed into the XTALN pin.
16
17, 18,
24, 25
PVDD
AIN1 to AIN4
Power
Input
PLL Power Supply (1.8 V).
Analog Video Input Channels.
19
VREFP
Output
Internal Voltage Reference Output.
20
VREFN
Output
Internal Voltage Reference Output.
21 AVDD
Power
Analog Power Supply (1.8 V).
22
DIAG1
Input
Diagnostic Input 1.
23
DIAG2
Input
Diagnostic Input 2.
26
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
27
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7281 circuitry.
28 ALSB Input This pin selects the I2C write address for the ADV7281. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
29
SDATA
Input/output I2C Port Serial Data Input/Output.
30 SCLK Input I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
31
PWRDWN
Input
Power-Down Pin. A logic low on this pin places the ADV7281 in power-down mode.
32 LLC
Output
Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but
it increases or decreases according to the video line length.
EPAD (EP)
Exposed Pad. The exposed pad must be connected to DGND.
Rev. B | Page 11 of 32

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