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ADIS16460 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADIS16460
Beschreibung Six Degrees of Freedom Inertial Sensor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 27 Seiten
ADIS16460 Datasheet, Funktion
Data Sheet
Compact, Precision,
Six Degrees of Freedom Inertial Sensor
ADIS16460
FEATURES
GENERAL DESCRIPTION
Triaxial digital gyroscope
Measurement range: ±100°/sec (minimum)
8°/hr (typical) in-run bias stability
0.12°/√hr (typical) angle random walk, x-axis
Triaxial digital accelerometer, ±5 g dynamic range
Autonomous operation and data collection
No external configuration commands required
Fast start-up time
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: 0°C ≤ TA ≤ 70°C
Serial peripheral interface (SPI) data communications
Data ready signal for synchronizing data acquisition
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Bartlett window finite impulse response (FIR) filter,
variable number of taps
External sample clock options: direct
Single command self test
Single-supply operation: 3.15 V to 3.45 V
2000 g shock survivability
Operating temperature range: −25°C to +85°C
The ADIS16460 iSensor® device is a complete inertial system
that includes a triaxial gyroscope and a triaxial accelerometer.
Each sensor in the ADIS16460 combines industry leading
iMEMS® technology with signal conditioning that optimizes
dynamic performance. The factory calibration characterizes
each sensor for sensitivity, bias, and alignment. As a result, each
sensor has its own dynamic compensation formulas that provide
accurate sensor measurements.
The ADIS16460 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation systems.
The SPI and register structures provide a simple interface for
data collection and configuration control.
The ADIS16460 is in an aluminum module package that is
approximately 22.4 mm × 22.4 mm × 9 mm and has a 14-pin
connector interface.
APPLICATIONS
Smart agriculture/construction machinery
Unmanned aerial vehicles (UAVs)/drones, and navigation
and payload stabilization
Robotics
Factory/industrial automation personnel/asset tracking
FUNCTIONAL BLOCK DIAGRAM
DR
SYNC
RST
VDD
SELF TEST
I/O
ALARMS
POWER
MANAGEMENT
GND
TRIAXIAL
GYROSCOPE
TRIAXIAL
ACCELEROMETER
TEMPERATURE
CONTROLLER
CALIBRATION
AND
FILTERS
CLOCK
ADIS16460
OUTPUT
DATA
REGISTERS
USER
CONTROL
REGISTERS
SPI
CS
SCLK
DIN
DOUT
Figure 1.
Rev. A
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ADIS16460 Datasheet, Funktion
Data Sheet
ADIS16460
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
tSTDR
tNV
t2
Description
Serial clock
Stall period between data
Read rate
Chip select to SCLK edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync to data ready valid transition
Data invalid time
Input sync period
1 Guaranteed by design and characterization, but not tested in production.
2 When using the burst read mode, the stall period is not applicable.
Normal Mode
Min1 Typ Max
0.1 2.0
16
24
200
25
25
50
5 12.5
5 12.5
0
25
636
47
500
Min1
0.1
N/A2
Burst Read
Typ Max
1.0
200
25
25
50
5 12.5
5 12.5
0
25
636
47
500
Timing Diagrams
CS
SCLK
tCS
1
DOUT
MSB
DIN R/W
tSCLKR
tSCLKF
23 4 5 6
tDAV
tDR
D14 D13 D12 D11 D10
tDSU
tDHD
tDF
A6 A5 A4 A3 A2
15 16
tSFS
D2 D1 LSB
DC2
DC1 LSB
Figure 2. SPI Timing and Sequence
tREADR ATE
tSTALL
CS
Unit
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
SCLK
CLOCK
Figure 3. Stall Time and Data Rate
t2
tSTDR
t1
DATA
READY
tNV
Figure 4. Input Clock Timing Diagram, MSC_CTRL[0] = 1
Rev. A | Page 5 of 26

6 Page









ADIS16460 pdf, datenblatt
Data Sheet
Burst Read Function
The burst read function provides a way to read all of the data in
one continuous stream of bits, with no stall time in between
each 16-bit segment. As shown in Figure 21, start this mode by
setting DIN = 0x3E00, and then read each of the following
registers out, while keeping CS low: DIAG_STAT,
X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT,
X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT,
SMPL_CNTR, and checksum. Use the following formula to
verify the checksum value, while treating each byte in the
formula as an independent, unsigned, 8-bit number.
Checksum = DIAG_STAT[15:8] + DIAG_STAT[7:0] +
X_GYRO_OUT[15:8] + X_GYRO_OUT[7:0] +
Y_GYRO_OUT[15:8] + Y_GYRO_OUT[7:0] +
Z_GYRO_OUT[15:8] + Z_GYRO_OUT[7:0] +
X_ACCL_OUT[15:8] + X_ACCL_OUT[7:0] +
Y_ACCL_OUT[15:8] + Y_ACCL_OUT[7:0] +
Z_ACCL_OUT[15:8] + Z_ACCL_OUT[7:0] +
TEMP_OUT[15:8] + TEMP_OUT[7:0] +
SMPL_CNTR[15:8] + SMPL_CNTR[7:0]
CS 1
23
11
SCLK
DIN 0x3E00
DOUT
DIAG_STAT XGYRO_OUT CHECKSUM
Figure 21. Burst Read Sequence
SPI Read Test Sequence
Figure 22 provides a test pattern for testing the SPI communica-
tion. In this pattern, write 0x5600 to the DIN line in a repeating
pattern and raise the chip select for a time that meets the stall
time requirement (see Table 2) each 16-bit sequence. Starting
with the second 16-bit sequence, DOUT produces the contents
of the PROD_ID register, 0x404C (see Table 41).
CS
SCLK
DIN DIN = 0101 0110 0000 0000 = 0x5600
DOUT
DOUT = 0100 0000 0100 1100 = 0x404C = 16,460
Figure 22. SPI Test Read Pattern DIN = 0x5600, DOUT = 0x404C
ADIS16460
DEVICE CONFIGURATION
The control registers in Table 8 provide users with a variety of
configuration options. The SPI provides access to these registers,
one byte at a time, using the bit assignments in Figure 20. Each
register has 16 bits, where Bits[7:0] represent the lower address,
and Bits[15:8] represent the upper address. Figure 23 provides
an example of writing 0x01 to Address 0x3E (GLOB_CMD[1],
using DIN = 0xBE01).
CS
SCLK
DIN
DIN = 1011 1110 0000 0001 = 0xBE01, WRITES 0x01 TO ADDRESS 0x3E.
Figure 23. Example SPI Write Sequence
Dual Memory Structure
Writing configuration data to a control register updates its
SRAM contents, which are volatile. After optimizing each
relevant control register setting in a system, set GLOB_CMD[3]
= 1 (DIN = 0xBE08) to copy these settings into nonvolatile flash
memory. The flash update process requires a valid power supply
level for the entire process time (see Table 44). Table 8 provides
a memory map for the user registers, which includes a flash
backup column. A yes in this column indicates that a register
has a mirror location in flash and, when backed up properly, it
automatically restores itself during startup or after a reset.
Figure 24 provides a diagram of the dual memory structure
used to manage operation and store critical user settings.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
Figure 24. SRAM and Flash Memory Diagram
Rev. A | Page 11 of 26

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