PDF ADP5589 Data sheet ( Hoja de datos )

Número de pieza	ADP5589
Descripción	Keypad Decoder and I/O Expansion
Fabricantes	Analog Devices
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Data Sheet Keypad Decoder and I/O Expansion ADP5589 FEATURES 16-element FIFO for event recording 19 configurable I/Os allowing functions such as Keypad decoding for matrix up to 11 × 8 Key press/release interrupts Key pad lock/unlock GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open drain Dual programmable logic blocks PWM generator Internal PWM generation External PWM with internal PWM AND function Clock divider Reset generators I2C interface with fast-mode plus (Fm+) support up to 1 MHz Open-drain interrupt output 24-lead LFCSP 3.5 mm × 3.5 mm 25-ball WLCSP 1.99 mm × 1.99 mm APPLICATIONS Devices requiring keypad entry and I/O expansion capabilities FUNCTIONAL BLOCK DIAGRAM VDD GND RST SDA SCL ADP5589 UVLO POR OSCILLATOR I2C INTERFACE R0 R1 R2 R3 R4 R5 R6 R7 C0 I/O C1 CONFIG C2 C3 C4 C5 C6 C7 C8 C9 C10 KEY SCAN AND DECODE GPI SCAN AND DECODE LOGIC 1 LOGIC 2 CLK DIV PWM RESET 1 GEN RESET 2 GEN Figure 1. REGISTERS INT GENERAL DESCRIPTION The ADP5589 is a 19 I/O port expander with built-in keypad matrix decoder, programmable logic, reset generator, and PWM generator. I/O expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs. The ADP5589, which handles all key scanning and decoding, can flag the main processor via an interrupt line when new key events have occurred. In addition, GPI changes and logic changes can be tracked as events via the FIFO, eliminating the need to monitor different registers for event changes. The ADP5589 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C compatible interface. The ADP5589 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions. The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, saving board area and cost. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADP5589 Data Sheet Parameter Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line Symbol tHD; STA tBUF tSU; STO tVD; DAT tVD; ACK tR tF tSP CB 6 Test Conditions/Comments Min 0.26 0.5 0.26 0 Typ Max 0.45 0.45 120 120 50 550 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V. 2 Maximum of five GPIOs active simultaneously. 3 All GPIOs active simultaneously. 4 Guaranteed by design. 5 All timers are referenced from the base oscillator and have the same ±10% accuracy. 6 CB is the total capacitance of one bus line in picofarads. Unit µs µs µs µs µs ns ns ns pF tF 70% SDA 30% SCL S SDA tSU; STA tR tSU; DAT 70% 30% tF tHD; DAT 70% 30% 70% 30% tHD; STA 1/fSCL FIRST CLOCK CYCLE tHD; STA tSP tR 70% 30% tLOW tHIGH tVD; DAT 70% 30% tBUF tVD; ACK tSU; STO SCL VIL = 0.3VDD VIH = 0.7VDD Sr 70% 30% NINTH CLOCK Figure 2. I2C Interface Timing Diagram P S NINTH CLOCK Rev. B \| Page 4 of 52 5 Page ADP5589 VDD KEY SCAN CONTROL C0 C1 C2 R0 R1 R2 123 45 6 78 9 3 × 3 KEYPAD MATRIX Figure 9. Simplified Key Scan Block Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low. The key scanner operates by checking the row pins to see if they are low. If Switch 6 in the matrix is pressed, R1 connects to C2. The key scan circuit senses that one of the row pins is pulled low, and a key scan cycle begins. Key scanning involves driving all column pins high, then driving each column pin, one at a time, low and sensing whether a row pin is low or not. All row/column pairs are Data Sheet scanned; therefore, if multiple keys are pressed, they are detected. To prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth. If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled up high. The key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. When the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode. For the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. A logic high level represents the key status as pressed, and a logic low represents released. This eliminates the need to draw individual row/column signals when describing key events. KEY PRESSED KEY x KEY RELEASED KEY RELEASED Figure 10. Logic Low: Released; Logic High: Pressed Figure 11 shows a detailed representation of the key scan block and its associated control and status signals. When all row and column pins are used, a matrix of 88 unique keys can be scanned. Rev. B \| Page 10 of 52 11 Page

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