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ADN4652 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN4652
Beschreibung Dual-Channel LVDS Isolators
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADN4652 Datasheet, Funktion
Data Sheet
5 kV RMS/3.75 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
ADN4650/ADN4651/ADN4652
FEATURES
5 kV rms/3.75 kV rms LVDS isolator
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS
Safety and regulatory approvals (20-lead SOIC package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 V peak
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
Operating temperature range: −40°C to +125°C
Choice of package and isolation options
3.75 kV rms in highly integrated 20-lead SSOP
5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance
APPLICATIONS
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
FUNCTIONAL BLOCK DIAGRAMS
VIN1
VIN2
ADN4650 LDO ISOLATION LDO
BARRIER
VDD1
VDD2
DIN1+
DIN1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT1+
DOUT1–
DOUT2+
DOUT2–
GND1
VDD1
VIN1
ADN4651 LDO
Figure 1.
ISOLATION
BARRIER
VIN2
LDO
GND2
DIN1+
DIN1–
DOUT2+
DOUT2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DOUT1+
DOUT1–
DIN2+
DIN2–
GND1
VDD1
VIN1
ADN4652 LDO
Figure 2.
ISOLATION
BARRIER
VIN2
LDO
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DIN1+
DIN1–
DOUT2+
DOUT2–
GENERAL DESCRIPTION
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers. This
technology allows drop-in isolation of an LVDS signal chain.
Multiple channel configurations are offered, and the LVDS receivers
on the ADN4651/ADN4652 include a fail-safe mechanism to
GND1
Figure 3.
GND2
ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead, wide
body SOIC package with 5 kV rms isolation or a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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ADN4652 Datasheet, Funktion
ADN4650/ADN4651/ADN4652
Data Sheet
PACKAGE CHARACTERISTICS
Table 6.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
20-Lead SOIC
20-Lead SSOP
Symbol Min Typ Max Unit Test Conditions/Comments
RI-O 1013
CI-O 2.2 pF f = 1 MHz
CI 3.7 pF
θJA Thermal simulation with 4-layer standard JEDEC PCB
45.7 °C/W
69.6 °C/W
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 7.
UL (Pending)
To Be Recognized Under UL 1577
Component Recognition
Program1
Single Protection, Isolation Voltage
20-lead SOIC, 5000 V rms
20-lead SSOP, 3750 V rms
File E214100
CSA (Pending)
To be approved under CSA
Component Acceptance Notice 5A
File 205078
VDE (Pending)
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, VIORM = 424 V peak, VIOSM = 6000 V peak
Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC) or ≥4500 V rms (20-lead SSOP)
for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 795 V peak for 1 sec (partial discharge
detection limit = 5 pC).
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 8.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Rev. D | Page 6 of 25
Symbol Characteristic Unit
VIORM
Vpd (m)
Vpd (m)
VIOTM
I to IV
I to IV
I to III
40/125/21
2
424
795
636
509
5000
V peak
V peak
V peak
V peak
V peak

6 Page









ADN4652 pdf, datenblatt
ADN4650/ADN4651/ADN4652
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, TA = 25°C, RL = 100 Ω, 300 MHz input with |VID| = 200 mV, and VIC = 1.1 V, unless otherwise noted.
70 70
60 60
50 50
40 40
30 30
20
10
0
0
IDD1
IDD2
IIN1
IIN2
50 100 150 200 250 300
INPUT CLOCK FREQUENCY (MHz)
Figure 9. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN1± Input Clock Frequency
(DIN2± Not Switching)
70
20
10
0
–50 –25
0
IDD1
IDD2
IIN1
IIN2
25 50 75 100 125
AMBIENT TEMPERATURE (°C)
Figure 12. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN2± with 300 MHz Clock Input, DIN1± Not Switching)
70
60 60
50 50
40 40
30
20
10
0
0
IDD1
IDD2
IIN1
IIN2
50 100 150 200 250 300
INPUT CLOCK FREQUENCY (MHz)
Figure 10. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN2± Input Clock Frequency
(DIN1± Not Switching)
70
30
20
10
0
2.35
IDD1 (DIN2 ACTIVE)
IDD2 (DIN2 ACTIVE)
IDD1 (DIN1 ACTIVE)
IDD2 (DIN1 ACTIVE)
2.40 2.45 2.50 2.55 2.60
SUPPLY VOLTAGE, VDD1/VDD2 (V)
2.65
Figure 13. IDD1/IDD2 Supply Current vs. Supply Voltage, VDD1/VDD2
70
60 60
50 50
40 40
30
20
10
0
–50 –25
0
IDD1
IDD2
IIN1
IIN2
25 50 75 100 125
AMBIENT TEMPERATURE (°C)
Figure 11. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN1± with 300 MHz Clock Input, DIN2± Not Switching)
30
20
10
0
3.00
IIN1 (DIN2 ACTIVE)
IIN2 (DIN2 ACTIVE)
IIN1 (DIN1 ACTIVE)
IIN2 (DIN1 ACTIVE)
3.15 3.30 3.45
SUPPLY VOLTAGE, VIN1/VIN2 (V)
3.60
Figure 14. IIN1/IIN2 Supply Current vs. Supply Voltage, VIN1/VIN2
Rev. D | Page 12 of 25

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