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PDF ADN4651 Data sheet ( Hoja de datos )
| Número de pieza | ADN4651 | |
| Descripción | Dual-Channel LVDS Isolators | |
| Fabricantes | Analog Devices | |
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Data Sheet
5 kV RMS/3.75 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
ADN4650/ADN4651/ADN4652
FEATURES
5 kV rms/3.75 kV rms LVDS isolator
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS
Safety and regulatory approvals (20-lead SOIC package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 V peak
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
Operating temperature range: −40°C to +125°C
Choice of package and isolation options
3.75 kV rms in highly integrated 20-lead SSOP
5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance
APPLICATIONS
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
FUNCTIONAL BLOCK DIAGRAMS
VIN1
VIN2
ADN4650 LDO ISOLATION LDO
BARRIER
VDD1
VDD2
DIN1+
DIN1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT1+
DOUT1–
DOUT2+
DOUT2–
GND1
VDD1
VIN1
ADN4651 LDO
Figure 1.
ISOLATION
BARRIER
VIN2
LDO
GND2
DIN1+
DIN1–
DOUT2+
DOUT2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DOUT1+
DOUT1–
DIN2+
DIN2–
GND1
VDD1
VIN1
ADN4652 LDO
Figure 2.
ISOLATION
BARRIER
VIN2
LDO
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DIN1+
DIN1–
DOUT2+
DOUT2–
GENERAL DESCRIPTION
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers. This
technology allows drop-in isolation of an LVDS signal chain.
Multiple channel configurations are offered, and the LVDS receivers
on the ADN4651/ADN4652 include a fail-safe mechanism to
GND1
Figure 3.
GND2
ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead, wide
body SOIC package with 5 kV rms isolation or a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Timing Diagram
DINx+
(DINx– = 1.2V)
VID
DOUTx+
+0.1V
ADN4650/ADN4651/ADN4652
>1.3V
1.2V
<1.1V
–0.1V
0V
~1.3V
DOUTx–
VOD
+0.1V
+0.1V
tFSH
tFSL
Figure 4. Fail-Safe Timing Diagram
~1.0V
~ +0.3V
0V
~ –0.3V
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 4. 20-Lead SOIC Package
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Table 5. 20-Lead SSOP Package
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Symbol
L (I01)
L (I02)
L (PCB)
CTI
Value
5000
7.8
7.8
8.1
17
>400
II
Unit
V rms
mm min
mm min
mm min
µm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Symbol
L (I01)
L (I02)
L (PCB)
CTI
Value
3750
5.3
5.3
5.6
22
>400
II
Unit
V rms
mm min
mm min
mm min
µm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. D | Page 5 of 25
5 Page 
Data Sheet
ADN4650/ADN4651/ADN4652
VIN1 1
GND1 2
VDD1 3
GND1 4
DOUT1+ 5
DOUT1– 6
DIN2+ 7
DIN2– 8
VDD1 9
GND1 10
ADN4652
TOP VIEW
(Not to Scale)
20 VIN2
19 GND2
18 VDD2
17 GND2
16 DIN1+
15 DIN1–
14 DOUT2+
13 DOUT2–
12 VDD2
11 GND2
Figure 8. ADN4652 Pin Configuration
Table 15. ADN4652 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using a 2.5
V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1
Ground, Side 1.
3, 9 VDD1
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO.
5
DOUT1+
Noninverted Differential Output 1.
6
DOUT1−
Inverted Differential Output 1.
7
DIN2+
Noninverted Differential Input 2.
8
11, 17, 19
DIN2−
GND2
Inverted Differential Input 2.
Ground, Side 2.
12, 18
VDD2
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO.
13
DOUT2−
Inverted Differential Output 2.
14
DOUT2+
Noninverted Differential Output 2.
15 DIN1− Inverted Differential Input 1.
16 DIN1+ Noninverted Differential Input 1.
20 VIN2
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using a 2.5
V supply, connect VIN2 directly to VDD2.
Rev. D | Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADN4651.PDF ] | |
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