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PDF ADAS1134 Data sheet ( Hoja de datos )
| Número de pieza | ADAS1134 | |
| Descripción | 24-Bit Current-to-Digital ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
128-Channel, 24-Bit Current-to-Digital ADC
ADAS1134
FEATURES
GENERAL DESCRIPTION
128-channel, low level current-to-digital converter
Up to 24-bit resolution
Up to 22.6 kSPS (44.2 µs integration time)
Simultaneous sampling
No dead time, no loss of charge
Ultralow noise down to 0.32 fC rms (2000 e−)
User adjustable full-scale range
INL: ±0.05% of reading of ±1.0 ppm FSRI
Low power dissipation: 2.25 mW per channel
The ADAS1134 is a 128-channel, current-to-digital, analog-to-
digital converter (ADC). It contains 128 low power, low noise,
low input current integrators, simultaneous sample-and-holds,
and two high speed, high resolution ADCs with configurable
sampling rate and resolutions up to 24 bits.
All converted channel results are output on a single, low voltage
differential signaling (LVDS), self clocked serial interface,
which reduces external hardware.
LVDS self clocked serial data interface
An SPI-compatible serial interface allows configuration of the
Serial peripheral interface (SPI) configuration registers
ADC using the SDI input. The SDO output allows the user to
(daisy-chain capability)
daisy-chain several ADCs on a single, 3-wire bus. The ADAS1134
On-board temperature sensor and reference buffer
10 mm × 10 mm, 242-ball CSP_BGA package
Low cost external components
Support tools
Evaluation board
uses IOVDD, a separate supply, to reduce digital noise effect on
the conversions.
The ADAS1134 is available in a 10 mm × 10 mm, 242-ball
CSP_BGA package.
Reference design with reference layout
FPGA Verilog code
APPLICATIONS
Medical, industrial, and security CT scanner data acquisition
Photodiode sensors
Dosimetry and radiation therapy systems
Optical fiber power monitoring
X-ray detection systems
High channel count data acquisition systems (current or
voltage inputs)
FUNCTIONAL BLOCK DIAGRAM
BUFPL
TO NEXT
2.5V 3.3V SDI
SDO
TO ALL ADCs
AN0
F
S/H
REF
CONFIGURATION
SCK
CS
RESET
AN63
AN64
AN127
KGND
F
S/H
F
S/H
F
S/H
+
–ADCL
SDI
DATA
PROCESSING
LVDS/CMOS
INTERFACE
+
–ADCH
TEMPERATURE
ADAS1134
SDI
DOUTx
CLKx
SYNC
IOVDD
IOGND
2.5V
FPGA
VIO
VT BUFPH
REF
2.048V
SDI FROM DOUT
FROM OF OTHER ADCs
PREVIOUS
SDO
Figure 1.
Rev. Sp0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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