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PDF ADAS1000-4 Data sheet ( Hoja de datos )
| Número de pieza | ADAS1000-4 | |
| Descripción | Three Electrode Electrocardiogram (ECG) Analog Front End | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Power, Three Electrode
Electrocardiogram (ECG) Analog Front End
ADAS1000-3/ADAS1000-4
FEATURES
Biopotential signals in; digitized signals out
3 acquisition (ECG) channels and one driven lead
Can be ganged for 8 electrode + RLD using master
ADAS1000 or ADAS1000-1
AC and DC lead-off detection
Internal pace detection algorithm on 3 leads
Support for user’s own pace
Thoracic impedance measurement (internal/external path)
Selectable reference lead
Scalable noise vs. power control, power-down modes
Low power operation from
11 mW (1 lead), 15 mW (3 leads)
Lead or electrode data available
Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38
R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005,
IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0
b:2005, IEC60601-2-51 ed. 1.0 b: 2005
Fast overload recovery
Low or high speed data output rates
Serial interface SPI-/QSPI™-/DSP-compatible
56-lead LFCSP package (9 mm × 9 mm)
64-lead LQFP package (10 mm × 10 mm body size)
APPLICATIONS
ECG: monitor and diagnostic
Bedside patient monitoring, portable telemetry, Holter,
AED, cardiac defibrillators, ambulatory monitors, pace
maker programmer, patient transport, stress testing
GENERAL DESCRIPTION
The ADAS1000-3/ADAS1000-4 measure electro cardiac (ECG)
signals, thoracic impedance, pacing artifacts, and lead-on/off
status and output this information in the form of a data frame
supplying either lead/vector or electrode data at programmable
data rates. Its low power and small size make it suitable for
portable, battery-powered applications. The high performance
also makes it suitable for higher end diagnostic machines.
The ADAS1000-4 is a full-featured, 3-channel ECG including
respiration and pace detection, while the ADAS1000-3 offers
only ECG channels with no respiration or pace features.
The ADAS1000-3/ADAS1000-4 are designed to simplify
the task of acquiring and ensuring quality ECG signals.
They provide a low power, small data acquisition system for
biopotential applications. Auxiliary features that aid in better
quality ECG signal acquisition include: multichannel averaged
driven lead, selectable reference drive, fast overload recovery,
flexible respiration circuitry returning magnitude and phase
information, internal pace detection algorithm operating
on three leads, and the option of ac or dc lead-off detection.
Several digital output options ensure flexibility when monitor-
ing and analyzing signals. Value-added cardiac post processing
is executed externally on a DSP, microprocessor, or FPGA.
Because ECG systems span different applications, the
ADAS1000-3/ADAS1000-4 feature a power/noise scaling
architecture where the noise can be reduced at the expense
of increasing power consumption. Signal acquisition channels
may be shut down to save power. Data rates can be reduced to
save power.
To ease manufacturing tests and development as well as offer
holistic power-up testing, the ADAS1000-3/ADAS1000-4
offer a suite of features, such as dc and ac test excitation via
the calibration DAC and CRC redundancy testing in addition
to readback of all relevant register address space.
The input structure is a differential amplifier input thereby
allowing users a variety of configuration options to best suit
their application.
The ADAS1000-3/ADAS1000-4 are available in two package
options: either a 56-lead LFCSP or a 64-lead LQFP package;
they are specified over −40°C to +85°C temperature range.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADAS1000-3/ADAS1000-4
SPECIFICATIONS
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA =
−40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external
regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%.
Front-end gain settings: GAIN 0 = ×1.4, GAIN 1 = ×2.1, GAIN 2 = ×2.8, GAIN 3 = ×4.2.
Table 2.
Parameter
ECG CHANNEL
Electrode Input Range
Input Bias Current
Input Offset
Min
0.3
0.63
0.8
0.97
−40
−200
Input Offset Tempco1
Input Amplifier Input
Impedance2
CMRR2
Crosstalk1
Resolution2
105
Integral Nonlinearity Error
Differential Nonlinearity Error
Gain2
GAIN 0 (×1.4)
GAIN 1 (×2.1)
GAIN 2 (×2.8)
GAIN 3 (×4.2)
Typ Max
1.3
1.3
1.3
1.3
±1
−7
−7
−15
−22
±2
1||10
110
80
19
18
16
30
5
4.9
9.81
39.24
3.27
6.54
26.15
2.45
4.9
19.62
1.63
3.27
13.08
2.3
1.97
1.8
1.63
+40
+200
Unit
V
V
V
V
nA
nA
mV
mV
mV
mV
μV/°C
GΩ||pF
dB
dB
Bits
Bits
Bits
ppm
ppm
µV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
μV/LSB
Test Conditions/Comments
These specifications apply to the following pins:
ECG1_LA, ECG2_LL, ECG3_RA, CM_IN (CE mode),
EXT_RESP_xx pins when used in extend switch mode
Independent of supply
GAIN 0 (gain setting ×1.4)
GAIN 1 (gain setting ×2.1)
GAIN 2 (gain setting ×2.8)
GAIN 3 (gain setting ×4.2)
Relates to each electrode input; over operating range;
dc and ac lead-off are disabled
AGND to AVDD
Electrode/vector mode with VCM = VCM_REF
GAIN 3
GAIN 2
GAIN 1
GAIN 0
At 10 Hz
51 kΩ imbalance, 60 Hz with ±300 mV differential dc
offset; per AAMI/IEC standards; with driven leg loop
closed
Between channels
Electrode/vector mode, 2 kHz data rate, 24-bit data-word
Electrode/vector mode, 16 kHz data rate, 24-bit data-
word
Electrode/analog lead mode, 128 kHz data rate, 16-bit
data-word
GAIN 0; all data rates
GAIN 0
Referred to input; (2 × VREF)/gain/(2N − 1); Applies
after factory calibration. User calibration adjusts this
number.
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
No factory calibration for this gain setting
At 19-bit level in 2 kHz data rate
At 18-bit level in 16 kHz data rate
At 16-bit level in 128 kHz data rate
Rev. B | Page 5 of 80
5 Page 
Data Sheet
ADAS1000-3/ADAS1000-4
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
Table 5.
Parameter1
Output Rate2
3.3 V
2
IOVDD
2.5 V
1.8 V
128
Unit
kHz
SCLK Cycle Time
tCSSA
tCSHA
tCH
tCL
tDO
tDS
tDH
tCSSD
tCSHD
tCSW
25
8.5
3
8
8
8.5
11
2
2
2
2
25
40 50
9.5 12
33
88
88
11.5 20
19 24
22
22
22
22
40 50
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
ns min
ns min
tDRDY_CS2
0 0 0 ns min
tCSO 6 7 9 ns typ
RESETE Low Time2 20 20 20 ns min
AA
Description
Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 37) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates.
See Table 21 for details on SCLK frequency vs. packet data/frame rates.
CSE valid setup time to rising SCLK.
AA
CSE valid hold time to rising SCLK.
AA
SCLK high time.
SCLK low time.
SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF.
SDI valid setup time from SCLK rising edge.
SDI valid hold time from SCLK rising edge.
CSE valid setup time from SCLK rising edge.
AA
CSE valid hold time from SCLK rising edge.
AA
CSE high time between writes (if used). Note that CSE is an optional input,
AA
AA
it may be tied permanently low. See a full description in the Serial
Interfaces section.
DRDYE to CSE setup time.
A A AA
Delay from CSE assert to SDO active.
AA
Minimum pulse width; RESETE is edge triggered.
AA
1 Guaranteed by characterization, not production tested.
2 Guaranteed by design, not production tested.
SCLK
CS
SDI
SDO
tCSHA
tCSSA
tCH tCL
tCSHD
tCSSD
MSB
DB[31]
tDS tDH
DB[30]
DB[29]
DB[25]
tCSW
DB[24]
DB[23]
DB[1]
DB[0]
LSB
tCSO
R/W
MSB
DRDY
DO_31
DO_30
ADDRESS
DO_29
DO_25
DATA
DO_1
LSB
DO_0
tDO
Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)
Rev. B | Page 11 of 80
11 Page | ||
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