PDF ADuCM310 Data sheet ( Hoja de datos )

Número de pieza	ADuCM310
Descripción	Precision Analog Microcontroller
Fabricantes	Analog Devices
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Data Sheet Precision Analog Microcontroller, Tunable Optical Control Microcontroller ADuCM310 FEATURES External 16 MHz crystal option Analog input/output 22-channel, 14-bit, 800 kSPS analog-to-digital converter (ADC) 10 external channels 1 on-chip die temperature monitor 6 current output digital-to-analog converter (IDAC) monitor channels 3 power monitor channels 2 buffered reference output channels Fully differential and single-ended modes 0 V to 2.5 V analog input range 6 low noise, 12-/14-bit IDAC outputs 1× 250 mA, 1× 200 mA, 2× 100 mA, and 2× 20 mA Semiconductor optical amplifier (SOA) IDAC pull-down to −3.0 V for fast current sink Eight 12-bit voltage output DACs (VDACs) Channel 0 and Channel 1: 0 V to 3 V, 75 Ω load Channel 2 and Channel 3: −5 V to 0 V, 500 Ω load Channel 4 and Channel 5: 0 V to 3 V, 300 Ω load Channel 6: 0 V to 5 V, 500 Ω load Channel 7: 0 V to 5 V, 100 Ω load 2.5 V, on-chip voltage reference 2 buffered 2.5 V outputs Microcontroller ARM Cortex-M3 processor, 32-bit RISC architecture Serial wire port supports code download and debugging Clocking options Trimmed on-chip oscillator (±3%) External clock source Memory 2× 128 kB Flash/EE memories, 32 kB SRAM In-circuit download, SW-DP-based debugging Software triggered in-circuit reprogrammability On-chip peripherals UART, 2× I2C and 2× SPI serial input/output 28-pin general-purpose input/output (GPIO) port 3 general-purpose timers Wake-up (W/U) timer Watchdog timer (WDT) 32-element programmable logic array (PLA) Vectored interrupt controller Interrupt on edge or level external pin inputs 9× external interrupts Power Multiple supplies 5 V for VDAC6 and VDAC7 3.3 V for digital and analog inputs/outputs 1.8 V to 2.7 V for IDACs −5 V supply for IDAC3 and VDAC2/VDAC3 Package and temperature range 6 mm × 6 mm, 112-ball CSP_BGA package Fully specified for −10°C to +85°C ambient operation Tools QuickStart™ development system Full third party support APPLICATIONS 80 MHz phase-locked loop (PLL) Optical modules—tunable laser modules FUNCTIONAL BLOCK DIAGRAM AIN0 AIN9 VREF_1.2 BUF_VREF2.5A BUF_VREF2.5B VDAC0 VDAC7 IDAC0 IDAC5 MUX BUF 14-BIT SAR ADC 32.786kHz 16MHz OSC 80MHz PLL INTERNAL CHANNELS, IDACs, TEMPERATURE, SUPPLIES 2.5V BAND GAP VREF VDAC VDAC IDAC IDAC ADuCM310 ARM CORTEX-M3 PROCESSOR MEMORY 256k FLASH 32k SRAM DMA NVIC PLA 32 × ELEMENTS POR ON-CHIP 1.8V LDO GPIO PORTS UART PORT 2 × SPI PORT 2 × I2C PORT EXT IRQs 3 × GP TIMER WD TIMER W/U TIMER PWM SERIAL WIRE RESET IOVDDx PVDD_IDACx AVDDx DGNDx PGND GENERAL- PURPOSE I/O PORTS SWDIO SWCLK Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADuCM310 Data Sheet SPECIFICATIONS AVDD = IOVDD = DVDD = 2.9 V to 3.6 V (the input supply voltages). The difference between AVDD, IOVDD, and DVDD must be ≤0.3 V. AVNEG (the supply voltage) = −5.5 V to −4.65 V. VDACVDD (the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7), and VDACVDD must be ≥ AVDD. PVDD (the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AVDD ≥ PVDD + 0.4V. VREF = 2.5 V internal reference, fCORE = 80 MHz, TA = −10°C to +85°C, unless otherwise noted. For power sequencing, apply power to the AVNEG or VDACVDD pin before connecting the ground pins. For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy Resolution Integral Nonlinearity Input Buffer Disabled Enabled Disabled Differential Nonlinearity DC Code Distribution ENDPOINT ERRORS Offset Error (All Channels Except the Internal Channels) Buffer On or Buffer Off Offset Error Drift1 Buffer On or Buffer Off Full-Scale Error Buffer On or Buffer Off Internal Channels Min 14 −0.99 −0.99 −0.6 −0.7 Gain Error Drift1 DYNAMIC PERFORMANCE1 Typ 5 ±1.5 ±2.5 ±1.5 ±0.7 ±0.7 ±3 ±0.2 ±2.5 ±0.2 ±0.2 0.75 2 Signal-to-Noise Ratio (SNR) Input Buffer Disabled Enabled 80 78 74 Max +1.5 +1.51 +0.6 +0.6 +0.6 1.5 Unit Test Conditions/Comments All measurements in single-ended mode, unless otherwise stated µs fSAMPLE ≥500 kSPS Bits LSB 2.5 V internal reference LSB LSB External reference LSB 2.5 V internal reference; no missing codes LSB 2.5 V external reference; no missing codes LSB ADC input voltage = 1.25 V dc ADC update rate up to 800 kSPS mV Buffer on, chop mode on and automatic zero or buffer off µV/°C mV % of full scale % of full scale µV/°C Buffer on, chop mode on and automatic zero or buffer off ADC update rate up to 800 kSPS Excluding internal channels Input buffer on; AVDD/2, IOVDD/2, PVDD voltage on PVDD_IDAC2 pin Input buffer on; IDAC0 to IDAC5; measured with 1.5 V on the IDAC0 to IDAC5 pins Full-scale error drift minus offset error drift; all modes; internal reference fIN = 665.283 Hz sine wave; fSAMPLE = 100 kSPS; internally unbuffered channels; the filter on the analog inputs is a 15 Ω resistor and a 2 nF capacitor dB Includes distortion and noise components dB Chop mode on dB Automatic zero Rev. A Page 4 of 27 5 Page ADuCM310 Parameter EXTERNAL RESET External Reset Minimum Pulse Width1 Reset Pin Glitch Immunity1 TEMPERATURE SENSOR Accuracy1 Min 1.5 1.25 Typ Max Unit µs 50 ns 1.37 1.494 V FLASH/EE MEMORY Endurance Data Retention INTERNAL HIGH POWER OSCILLATOR 10,000 20 Accuracy INTERNAL LOW POWER OSCILLATOR Accuracy LOGIC INPUTS Input Low Voltage (VINL) Input High Voltage (VINH) Short-Circuit Current1 LOGIC OUTPUTS Output High Voltage (VOH)10 Output Low Voltage (VOL)10 Short-Circuit Current1 INPUT LEAKAGE CURRENT Logic 1 Internal Pull-Up Disabled Logic 0 Internal Pull-Up Disabled Pull-Up −2.25 −12 0.7 × IOVDD IOVDD − 0.4 −20 −20 30 16 32.768 ±8 80 +6 80 +6 40 CRYSTAL INPUTS XCLKI AND XCLKO (16 MHz) Logic Inputs, XCLKI Only Input Low Voltage (VINL) Input High Voltage (VINH) XCLKI Input Capacitance XCLKO Output Capacitance MICROCONTROLLER UNIT CLOCK RATE Using PLL Output1 PROCESSOR START-UP TIME At Power-On1 0.05 After Reset Event After Processor Power Down Mode 1, Mode 2, or Mode 3 1.1 1.7 8 8 38 1.44 3 to 5 +2.25 +12 Cycles Years MHz % kHz % 0.2 × IOVDD 12 V V mA V 0.4 V 12 mA µA +20 nA µA +20 nA 65 kΩ V V pF pF 80 MHz 50 ms ms fCLK Data Sheet Test Conditions/Comments Minimum pulse width required on external RESET pin to trigger a reset sequence Maximum low pulse width on RESET pin that does not generate a reset Indicates die temperature; ADC measured voltage for temperature sensor channel without calibration, TA = 25°C TJ = 85°C Used as input to PLL to generate 80 MHz clock ISOURCE = 2 mA ISINK = 2 mA VINH = 3.6 V VINH = 0 V If not disabled, disabled at reset; pull-up can be described as an 80 µA (typical) current source Includes kernel power-on execution time Includes kernel power-on execution time Rev. A Page 10 of 27 11 Page

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