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ADF4153A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4153A
Beschreibung Fractional-N Frequency Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADF4153A Datasheet, Funktion
Data Sheet
Fractional-N Frequency Synthesizer
ADF4153A
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4153A
REFIN
MUXOUT
×2
DOUBLER
4-BIT
R COUNTER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
THIRD ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CURRENT
SETTING
CP
RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. A
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Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADF4153A Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V,
VDD = AVDD = DVDD = SDVDD, unless otherwise noted.
Table 3.
Parameter
VDD to GND
DVDD to AVDD
SDVDD to AVDD
VP to GND
VP to VDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFIN to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +125°C
150°C
112°C/W
30.4°C/W
260°C
40 sec
ADF4153A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. A | Page 5 of 24

6 Page









ADF4153A pdf, datenblatt
Data Sheet
ADF4153A
9-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FL1 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0)
F12 F11 F10
F3 F2 F1 FRACTIONAL VALUE (FRAC)
0 0 0 .......... 0 0 0 0
0 0 0 .......... 0 0 1 1
0 0 0 .......... 0 1 0 2
0 0 0 .......... 0 1 1 3
. . . .......... . . . .
. . . .......... . . . .
. . . .......... . . . .
1 1 1 .......... 1 0 0 4092
1 1 1 .......... 1 0 1 4093
1 1 1 .......... 1 1 0 4094
1 1 1 .......... 1 1 1 4095
N9 N8
00
00
00
00
..
..
..
11
11
11
N7 N6 N5 N4 N3 N2 N1
0 011 111
0 100 000
0 100 001
0 100 010
. ... ...
. ... ...
. . . ... . . .
1 111 101
1 111 110
1 111 111
INTEGER VALUE (INT)
31
32
33
34
.
.
.
509
510
511
FL1 FASTLOCK
0 NORMAL OPERATION
1 FASTLOCK ENABLED
Figure 17. N Divider Register Map (R0)
Rev. A | Page 11 of 24

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