PDF ADN4670 Data sheet ( Hoja de datos )

Número de pieza	ADN4670
Descripción	Programmable Low Voltage 1:10 LVDS Clock Driver
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet FEATURES Low output skew <30 ps (typical) Distributes one differential clock input to 10 LVDS clock outputs Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock outputs enabled/disabled Signaling rate up to 1.1 GHz (typical) 2.375 V to 2.625 V power supply range ±100 mV differential input threshold Input common-mode range from rail-to-rail I/O pins fail-safe during power-down: VDD = 0 V Available in 32-lead LFCSP and LQFP packages Industrial operating temperature range: −40°C to +85°C APPLICATIONS Clock distribution networks GENERAL DESCRIPTION The ADN4670 is a low voltage differential signaling (LVDS) clock driver that expands a differential clock input signal to 10 differential clock outputs. The device is programmable using a simple serial interface, so that one of two clock inputs can be selected (CLK0/CLK0 or CLK1/CLK1) and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled (tristated). The ADN4670 is designed for use in 50 Ω transmission line environments. When the enable input EN is high, the device may be pro- grammed by clocking 11 data bits into the shift register. The Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670 FUNCTIONAL BLOCK DIAGRAM CK SI 11-BIT SHIFT REGISTER EN CLK0 CLK0 CLK1 CLK1 11-BIT CONTROL REGISTER 10 9 8 7 6 5 4 3 2 1 0 MUX 1 0 0 1 MUX Figure 1. 12-BIT COUNTER Q9 Q9 Q8 Q8 Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). A 12th clock pulse transfers data from the shift register to the control register. The ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead LFCSP and LQFP packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. 1 page ADN4670 Data Sheet LVDS SWITCHING CHARACTERISTICS VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Propagation Delay Low to High Propagation Delay High to Low Duty Cycle Output Skew2 Pulse Skew3 Part-to-Part Output Skew4 Output Rise Time Output Fall Time Maximum Input Frequency Symbol tPLHx tPHLx tDUTY tSK(O) tSK(P) tSK(PP) tr tf fCLK Min 45 900 Typ 2 2 30 1100 Max1 Unit Conditions/Comments 3 ns From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx 3 ns From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx 55 % From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx ps Any Qx/Qx 50 ps Any Qx/Qx 600 ps Any Qx/Qx 350 ps Any Qx/Qx, 20% to 80%, RL = 100 Ω CL = 5 pF 350 Any Qx/Qx, 80% to 20%, RL = 100 Ω CL = 5 pF MHz From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx 1 Guaranteed by design and characterization. 2 Output skew is defined as the difference between the largest and smallest values of TPLHx within a device or the difference between the largest and smallest values of TPHLx within a device, whichever of the two is greater. 3 Pulse skew is defined as the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, \|tPHLx – tHLPx\|. 4 Part-to-part output skew is defined as the difference between the largest and smallest values of TPLHx across multiple devices or the difference between the largest and smallest values of TPHLx across multiple devices, whichever of the two is greater. CLK CLK Q0 Q0 Q1 Q1 tPLH0 tPLH1 tPHL0 tPHL1 Q9 Q9 tPLH9 tPHL9 Figure 2. Waveforms for Calculation of tSK(O) and tSK(PP) Rev. A \| Page 4 of 12 5 Page ADN4670 NOTES Data Sheet Rev. A \| Page 10 of 12 11 Page

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