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AD9523-1 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9523-1
Beschreibung Low Jitter Clock Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9523-1 Datasheet, Funktion
Data Sheet
Low Jitter Clock Generator with
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9523-1
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
Dual VCO dividers
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <150 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Broadband timing jitter: 124 fs
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC_IN, OSC_IN
AD9523-1
PLL1
PLL2
DIVIDE-BY-
3, 4, 5
8 OUTPUTS
OUT0,
OUT0
OUT3,
OUT3
OUT10,
OUT10
OUT13,
OUT13
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
DIVIDE-BY-
3, 4, 5
ZERO
DELAY
EEPROM
6 OUTPUTS
14-CLOCK
DISTRIBUTION
ZD_IN, ZD_IN
Figure 1.
OUT4,
OUT4
OUT9,
OUT9
GENERAL DESCRIPTION
The AD9523-1 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO with two VCO dividers. The on-chip VCO
tunes from 2.94 GHz to 3.1 GHz.
The AD9523-1 is designed to support the clock requirements
for long term evolution (LTE) and multicarrier GSM base
station designs. It relies on an external VCXO to provide the
reference jitter cleanup to achieve the restrictive low phase noise
requirements necessary for acceptable data converter SNR
performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free, coarse timing adjustment
in increments that are equal to half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9523-1 Datasheet, Funktion
Data Sheet
AD9523-1
Parameter
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
Min Typ Max Unit Test Conditions/Comments
20 24.2 mA f = 122.88 MHz
50 59.1 mA f = 983.04 MHz
14 16.7 mA f = 122.88 MHz
42.5 49
mA f = 983.04 MHz
2 2.4 mA f = 15.36 MHz, 10 pF Load
Channel x control register, Bit 4 = 1
10 10.8 mA f = 122.88 MHz
27 29.8 mA f = 983.04 MHz
6.5 7.5 mA f = 122.88 MHz
23 26.3 mA f = 983.04 MHz
11 12.4 mA f = 122.88 MHz
28 31.2 mA f = 983.04 MHz
20 24.3 mA f = 122.88 MHz
50 59.1 mA f = 983.04 MHz
11 12.7 mA f = 122.88 MHz
27 31.8 mA f = 983.04 MHz
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
Rev. C | Page 5 of 63

6 Page









AD9523-1 pdf, datenblatt
Data Sheet
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 13.
Parameter
VOLTAGE
Output High
Output Low
Min
2.94
Typ
AD9523-1
Max Unit Test Conditions/Comments
V
0.4 V
SERIAL CONTROL PORT—SPI MODE
Table 14.
Parameter
CS (INPUT)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Min
Input Capacitance
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
2.7
8
12
3.3
0
10
0
6
Typ Max
2.0
0.8
30
−110
2
2.0
0.8
240
1
2
Unit Test Conditions/Comments
CS has an internal 40 kΩ pull-up resistor
V
V
µA
µA The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9523-1
pF
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
V
V
µA
µA
pF
2.0 V
0.8 V
1 µA
1 µA
2 pF
V
0.4 V
25 MHz
ns
ns
ns
ns
14 ns
ns
ns
ns
Rev. C | Page 11 of 63

12 Page





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