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AD9530 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9530
Beschreibung Low Jitter Clock Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9530 Datasheet, Funktion
Data Sheet
4 CML Output, Low Jitter Clock Generator
with an Integrated 5.4 GHz VCO
AD9530
FEATURES
Fully integrated, ultralow noise phase-locked loop (PLL)
4 differential, 2.7 GHz common-mode logic (CML) outputs
2 differential reference inputs with programmable internal
termination options
<232 fs rms absolute jitter (12 kHz to 20 MHz) with a non-
ideal reference and 8 kHz loop bandwidth
<100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz
loop bandwidth and low jitter input reference clock
Supports low loop bandwidths for jitter attenuation
Manual switchover
Single 2.5 V typical supply voltage
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
40 Gbps/100 Gbps optical transport network (OTN) line side
clocking
Clocking of high speed analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs)
Data communications
GENERAL DESCRIPTION
The AD9530 is a fully integrated PLL and distribution supporting,
clock cleanup, and frequency translation device for 40 Gbps/
100 Gbps OTN applications. The internal PLL can lock to one
of two reference frequencies to generate four discrete output
frequencies up to 2.7 GHz.
The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow
noise voltage controlled oscillator (VCO). All four outputs are
individually divided down from the internal VCO using two high
speed VCO dividers (the Mx dividers) and four individual 8-bit
channel dividers (the Dx dividers). The high speed VCO dividers
offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of
possible output frequencies. The AD9530 is configurable for
loop bandwidths <15 kHz to attenuate reference noise.
The AD9530 is available in a 48-lead LFCSP and operates from a
single 2.5 V typical supply voltage.
The AD9530 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
AD9530
REFA
REFA
REFB
REFB
800MHz MAX
R DIVIDER
(1 TO 255)
PLL
SERIAL PORT AND
CONTROL LOGIC
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
D1 DIVIDER
(1 TO 255)
D2 DIVIDER
(1 TO 255)
D3 DIVIDER
(1 TO 255)
D4 DIVIDER
(1 TO 255)
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
SDIO SDO SCLK CS
LD
Figure 1.
CML 50Ω SOURCE TERMINATED
2.7GHz MAX
Rev. 0
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Tel: 781.329.4700
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Technical Support
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AD9530 Datasheet, Funktion
Data Sheet
AD9530
Parameter
CURRENT DELTAS, INDIVIDUAL FUNCTIONS
VCO High Performance Mode Enabled
REFx/REFx Receiver1
Reference Divider
Output Channel
Min Typ Max Unit
133.5 160.0 mA
2.5 3.3 mA
−0.55 −0.39
mA
28.4 33.3 mA
Mx Divider On/Off
Single Output Plus Associated Channel Divider
(OUT1: Pin 31, OUT2: Pin 35, OUT3: Pin 41,
OUT4: Pin 45)
33.2 36.2 mA
28.4 33.4 mA
Test Conditions/Comments
Current delta when a function is enabled/disabled
from Typical Operation 1
Current increase when the VCO mode is changed
from low power mode to high performance mode;
combined current delta of Pin 20 to Pin 23
Current increase when REFB is enabled with a
110.42 MHz reference input; combined current
delta of Pin 3 and Pin 7
Delta from bypassing reference divider to using
reference divider = 2; total feedback division
doubled to preserve lock; combined current delta
of Pin 3 and Pin 7
One output channel enabled by powering up
M2 divider = 3; D3 and D4 divider = 1; OUT3 and
OUT4 enabled to 800 mV; no internal termination;
associated low-dropout regulators (LDOs)
enabled; includes the current required by the
external termination; both outputs at 1766.72 MHz
This is the current consumption delta between
an Mx (where x is 0, 1, or 2) divider powered up
and powered down; these dividers are a part of
the RTWO VDD (Pin 20 to Pin 23) power domain
One output driver enabled by powering up the
driver and channel divider (does not include
power on the extra M2 divider); includes the
current required by the external termination;
output = 1766.72 MHz
1 Where x is either A or B.
POWER DISSIPATION SPECIFICATIONS
Table 3.
Parameter
TOTAL POWER DISSIPATION
Min
Power-On Default
Power-Down Mode
Typical Operation 2
All Blocks Running
800 mV Output Swing, Without
Internal Output Termination
1100 mV Output Swing with Internal
Output Termination
Typ
2.284
0.338
2.344
2.536
2.796
Max Unit
2.750
0.480
2.82
W
W
W
3.02 W
3.326 W
Test Conditions/Comments
Does not include power dissipated in external resistors;
all CML outputs terminated with 50 Ω to VDD; internal
output termination is disabled; output amplitude set
to 1.0 V; reference inputs set to ac-coupled mode
fRTWO = 5302.5 MHz; VCO mode = high performance;
REFA enabled at 101 MHz, ac-coupled; REFB disabled;
R divider = 1; M1 divider and M3 divider = 2.5;
PFD = 101 MHz; OUT1 and OUT2 CML outputs at
2121 MHz; OUT3 and OUT4 disabled; output swing
level = 800 mV; outputs terminated externally to 50 Ω
to VDD and internal termination disabled; M2 divider
and LDO powered down; D3 and D4 dividers and
associated LDOs disabled
fRTWO = 5400 MHz; VCO mode = high performance;
REFA and REFB enabled at 100 MHz; ac-coupled mode;
R divider = 1; M divider = 2; PFD = 100 MHz; four CML
outputs at 2700 MHz
Single-ended output swing level = 800 mV and
internal termination off
Single-ended output swing level = 1100 mV and
internal termination on
Rev. 0 | Page 5 of 41

6 Page









AD9530 pdf, datenblatt
Data Sheet
AD9530
Parameter
SDIO (INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Voltage
Logic 1
Logic 0
TIMING
Clock Rate (SCLK)
Pulse Width High
Pulse Width Low
SDIO to SCLK Setup
SCLK to SDIO Hold
SCLK to Valid SDIO and SDO
CS to SCLK Setup
CS to SCLK Hold
CS Minimum Pulse Width High
Symbol
1/tSCLK
tHIGH
tLOW
tDS
tDH
tDV
tS
tH
tPWH
Min Typ
VDD − 0.4
1
1
3
VDD − 0.2
6
6
1.8
0.6
0.6
3.5
1.5
Max Unit Test Conditions/Comments
V
0.4 V
µA
µA
pF
1 mA load current
V
0.2 V
See Figure 26 through Figure 30 and Table 21
40 MHz
ns
ns
ns
ns
10 ns
ns
ns
ns
Rev. 0 | Page 11 of 41

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