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ADRF5130 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADRF5130
Beschreibung Reflective Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 11 Seiten
ADRF5130 Datasheet, Funktion
Data Sheet
High Power, 44 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 3.5 GHz
ADRF5130
FEATURES
Reflective, 50 Ω design
Low insertion loss: 0.6 dB typical to 2.0 GHz
High isolation: 50 dB typical to 2.0 GHz
High power handling
RF input power, continuous wave (CW) at TCASE = 85°C
43 dBm maximum operating
46.5 dBm absolute maximum rating
High linearity
0.1 dB compression (P0.1dB): 46 dBm typical
Input third-order intercept (IP3): 68 dBm typical to 2 GHz
ESD ratings
Human body model (HBM): 2 kV, Class 2
Charged device model (CDM): 1.25 kV
Single positive supply: VDD = 5 V
Positive control, TTL-compatible: VCTL = 0 V or VDD
24-lead, 4 mm × 4 mm LFCSP package (16 mm2)
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
GENERAL DESCRIPTION
The ADRF5130 is a high power, reflective, 0.7 GHz to 3.5 GHz,
silicon, single-pole, double-throw (SPDT) switch in a leadless,
surface-mount package. The switch is ideal for high power and
cellular infrastructure applications, like long-term evolution (LTE)
base stations. The ADRF5130 has high power handling of 43 dBm
(maximum), a low insertion loss of 0.6 dB, input third-order
intercept of 68 dBm (typical), and 0.1 dB compression (P0.1dB)
FUNCTIONAL BLOCK DIAGRAM
VCTL
ADRF5130
RF1 RF2
RFC
Figure 1.
of 46 dBm. On-chip circuitry operates at a single, positive
supply voltage of 5 V and typical supply current of 1.06 mA,
making the ADRF5130 an ideal alternative to pin diode-based
switches.
The device comes in a RoHS compliant, compact, 24-lead, 4 mm ×
4 mm LFCSP package.
Rev. A
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ADRF5130 Datasheet, Funktion
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADRF5130
GND 1
GND 2
RF1 3
GND 4
GND 5
GND 6
ADRF5130
TOP VIEW
(Not to Scale)
18 GND
17 GND
16 RF2
15 GND
14 GND
13 GND
PACKAGE
BASE
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1, 2, 4 to 9, 11 to 15, 17 to 20, 23, 24 GND
3 RF1
10 RFC
16 RF2
21 VCTL
22 VDD
EPAD
Description
Ground. The package bottom has an exposed metal pad that must connect to the
printed circuit board (PCB) RF/dc ground. See Figure 3 for the GND interface schematic.
RF Output Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor
is required on this pin.
RF Input Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking
capacitor is required on this pin.
RF Output Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor
is required on this pin.
Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 4 and the
recommended digital input control voltage range in Table 1.
Supply Voltage. See Figure 4 for the VDD interface schematic.
Exposed Pad. Exposed pad must be connected to RF/dc ground.
Table 4. Truth Table
Control Input (VCTL) State
Low
High
INTERFACE SCHEMATICS
RFC to RF1
Off
On
GND
Figure 3. GND Interface Schematic
Signal Path State
RFC to RF2
On
Off
VDD
VCTL
Figure 4. Control Interface Schematic
Rev. A | Page 5 of 10

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