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ADF7023 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF7023
Beschreibung ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADF7023 Datasheet, Funktion
Data Sheet
High Performance, Low Power, ISM Band
FSK/GFSK/OOK/MSK/GMSK Transceiver IC
ADF7023
FEATURES
Ultralow power, high performance transceiver
Frequency bands
862 MHz to 928 MHz
431 MHz to 464 MHz
Data rates supported
1 kbps to 300 kbps
2.2 V to 3.6 V power supply
Single-ended and differential PAs
Low IF receiver with programmable IF bandwidths
100 kHz, 150 kHz, 200 kHz, 300 kHz
Receiver sensitivity (BER)
−116 dBm at 1.0 kbps, 2FSK, GFSK
−107.5 dBm at 38.4 kbps, 2FSK, GFSK
−102.5 dBm at 150 kbps, GFSK, GMSK
−100 dBm at 300 kbps, GFSK, GMSK
−104 dBm at 19.2 kbps, OOK
Very low power consumption
12.8 mA in PHY_RX mode (maximum front-end gain)
24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)
0.75 µA in PHY_SLEEP mode (32 kHz RC oscillator active)
1.28 µA in PHY_SLEEP mode (32 kHz XTAL oscillator active)
0.33 µA in PHY_SLEEP mode (Deep Sleep Mode 1)
RF output power of −20 dBm to +13.5 dBm (single-ended PA)
RF output power of −20 dBm to +10 dBm (differential PA)
Patented fast settling automatic frequency control (AFC)
Digital received signal strength indication (RSSI)
Integrated PLL loop filter and Tx/Rx switch
Fast automatic VCO calibration
Automatic synthesizer bandwidth optimization
On-chip, low-power, custom 8-bit processor
Radio control
Packet management
Smart wake mode
Packet management support
Highly flexible for a wide range of packet formats
Insertion/detection of preamble/sync word/CRC/address
Manchester and 8b/10b data encoding and decoding
Data whitening
Smart wake mode
Current saving low power mode with autonomous receiver
wake up, carrier sense, and packet reception
Downloadable firmware modules
Image rejection calibration, fully automated (patent pending)
128-bit AES encryption/decryption with hardware
acceleration and key sizes of 128 bits, 192 bits, and
256 bits
Reed Solomon error correction with hardware acceleration
240-byte packet buffer for TX/RX data
Efficient SPI control interface with block read/write access
Integrated battery alarm and temperature sensor
Integrated RC and 32.768 kHz crystal oscillator
On-chip, 8-bit ADC
5 mm × 5 mm, 32-pin, LFCSP package
APPLICATIONS
Smart metering
IEEE 802.15.4g
Wireless MBUS
Home automation
Process and building control
Wireless sensor networks (WSNs)
Wireless healthcare
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.






ADF7023 Datasheet, Funktion
ADF7023
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
ADCIN_ATB3
RFIO_1P
RFIO_1N
RFO2
LNA
PA
RSSI/
LOGAMP
8-BIT
ADC
FSK
ASK
DEMOD
CDR
AFC
AGC
8-BIT RISC
PROCESSOR
4kB ROM
MAC
2kB RAM
256 BYTE
PACKET
RAM
PA DIVIDER
LOOP
FILTER
CHARGE
PUMP
PFD
26MHz OSC
64 BYTE
BBRAM
256 BYTE
MCR RAM
PA RAMP
PROFILE
ADF7023
DIVIDER
Σ-Δ
MODULATOR
fDEV
GAUSSIAN
FILTER
WAKE-UP CONTROL
TIMER UNIT
IRQ
CTRL
SPI
GPIO
TEST
DAC
CLOCK
DIVIDER
BIAS
ANALOG
TEST
TEMP
SENSOR
BATTERY
MONITOR
32kHz
OSC
32kHz
RCOSC
26MHz
OSC
IRQ_GP3
CS
MISO
SCLK
MOSI
GPIO1
CREGRFx CREGVCO CREGSYNTH CREGDIGx RBIAS
1GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27.
XOSC32KN_ATB2 XOSC32KP_GP5_ATB1 XOSC26N XOSC26P
Figure 1.
GENERAL DESCRIPTION
The ADF7023 is a very low power, high performance, highly
integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed
for operation in the 862 MHz to 928 MHz and 431 MHz to
464 MHz frequency bands, which cover the worldwide license-
free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable
for circuit applications that operate under the European ETSI
EN300-220, the North American FCC (Part 15), the Chinese short-
range wireless regulatory standards, or other similar regional
standards. Data rates from 1 kbps to 300 kbps are supported.
The transmit RF synthesizer contains a VCO and a low noise
fractional-N PLL with an output channel frequency resolution
of 400 Hz. The VCO operates at 2× or 4×, the fundamental
frequency to reduce spurious emissions. The receive and transmit
synthesizer bandwidths are automatically, and independently,
configured to achieve optimum phase noise, modulation quality,
and settling time. The transmitter output power is programmable
from −20 dBm to +13.5 dBm, with automatic PA ramping to
meet transient spurious specifications. The part possesses both
single-ended and differential PAs, which allows for Tx antenna
diversity.
The receiver is exceptionally linear, achieving an IP3 specification
of −12.2 dBm and −11.5 dBm at maximum gain and minimum
gain, respectively, and an IP2 specification of 18.5 dBm and
27 dBm at maximum gain and minimum gain, respectively. The
receiver achieves an interference blocking specification of 66 dB
at ±2 MHz offset and 74 dB at ±10 MHz offset. Thus, the part is
extremely resilient to the presence of interferers in spectrally
noisy environments. The receiver features a novel, high speed,
automatic frequency control (AFC) loop, allowing the PLL to
find and correct any RF frequency errors in the recovered packet.
A patent pending, image rejection calibration scheme is available
through a program download. The algorithm does not require
the use of an external RF source nor does it require any user
intervention once initiated. The results of the calibration can be
stored in nonvolatile memory for use on subsequent power-ups
of the transceiver.
The ADF7023 operates with a power supply range of 2.2 V to
3.6 V and has very low power consumption in both Tx and Rx
modes, enabling long lifetimes in battery-operated systems
while maintaining excellent RF performance. The device can
enter a low power sleep mode in which the configuration
settings are retained in BBRAM.
The ADF7023 features an ultralow power, on-chip,
communications processor. The communications processor,
which is an 8-bit RISC processor, performs the radio control,
packet management, and smart wake mode (SWM) functionality.
The communications processor eases the processing burden of
the companion processor by integrating the lower layers of a
typical communication protocol stack. The communications
processor also permits the download and execution of a set of
firmware modules that include image rejection (IR) calibration,
AES encryption, and Reed Solomon coding.
The communications processor provides a simple command-based
radio control interface for the host processor. A single-byte
command transitions the radio between states or performs a
radio function.
Rev. C | Page 4 of 112

6 Page









ADF7023 pdf, datenblatt
ADF7023
Parameter
LNA AND MIXER, 1 dB COMPRESSION
POINT
Max LNA Gain, Max Mixer Gain
Min LNA Gain, Min Mixer Gain
ADJACENT CHANNEL REJECTION
CW Interferer
Min Typ
−21.9
−21
200 kHz Channel Spacing
300 kHz Channel Spacing
400 kHz Channel Spacing
600 kHz Channel Spacing
Modulated Interferer
38
39
38
40
41
200 kHz Channel Spacing
300 kHz Channel Spacing
300 kHz Channel Spacing
400 kHz Channel Spacing
600 kHz Channel Spacing
CO-CHANNEL REJECTION
BLOCKING
38
36
36
34
35
−4
RF Frequency = 433 MHz
±2 MHz
±10 MHz
RF Frequency = 868 MHz
±2 MHz
±10 MHz
RF Frequency = 915 MHz
±2 MHz
±10 MHz
68
76
66
74
66
74
Data Sheet
Max Unit Test Conditions
RF frequency = 915 MHz
dBm
dBm
Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), CW interferer power level increased until
BER = 10−3, image calibrated
dB IF BW = 100 kHz, wanted signal: FDEV = 12.5 kHz,
DR = 50 kbps
dB IF BW = 100 kHz, wanted signal: FDEV = 25 kHz,
DR = 100 kbps
dB IF BW = 150 kHz, wanted signal: FDEV = 37.5 kHz,
DR = 150 kbps
dB IF BW = 200 kHz, wanted signal: FDEV = 50 kHz,
DR = 200 kbps
dB IF BW = 300 kHz, wanted signal: FDEV = 75 kHz,
DR = 300 kbps
Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), modulated interferer with the same
modulation as the wanted signal; interferer power
level increased until BER = 10−3, image calibrated
dB IF BW = 100 kHz, wanted signal: FDEV = 12.5 kHz,
DR = 50 kbps
dB IF BW = 100 kHz, wanted signal: FDEV = 25 kHz,
DR = 100 kbps
dB IF BW = 150 kHz, wanted signal: FDEV = 37.5 kHz,
DR = 150 kbps
dB IF BW = 200 kHz, wanted signal: FDEV = 50 kHz,
DR = 200 kbps
dB IF BW = 300 kHz, wanted signal: FDEV = 75 kHz,
DR = 300 kbps
dB Desired signal 10 dB above the input sensitivity level
(BER = 10−3), data rate = 38.4 kbps, frequency deviation
= 20 kHz, RF frequency = 868 MHz
Desired signal 3 dB above the input sensitivity level
(BER = 10−3) of −107.5 dBm (data rate = 38.4 kbps),
modulated interferer power level increased until BER =
10−3 (see the Typical Performance Characteristics
section for blocking at other offsets and IF
bandwidths)
dB
dB
dB
dB
dB
dB
Rev. C | Page 10 of 112

12 Page





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