PDF ADRF6620 Data sheet ( Hoja de datos )

Número de pieza	ADRF6620
Descripción	700 MHz to 2700 MHz Rx Mixer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 700 MHz to 2700 MHz Rx Mixer with Integrated IF DGA, Fractional-N PLL, and VCO ADRF6620 FEATURES Integrated fractional-N phase-locked loop (PLL) RF input frequency range: 700 MHz to 2700 MHz Internal local oscillator (LO) frequency range: 350 MHz to 2850 MHz Input P1dB: 17 dBm Output IP3: 45 dBm Single-pole four-throw (SP4T) RF input switch Digital step attenuator (DSA) range: 0 dB to 15 dB Integrated RF tunable balun allowing single-ended 50 Ω input Multicore integrated voltage controlled oscillator (VCO) Digitally programmable variable gain amplifier (DGA) −3 dB bandwidth: >600 MHz Balanced 150 Ω IF output impedance Programmable via 3-wire serial port interface (SPI) Single 5 V supply APPLICATIONS Wireless receivers Digital predistortion (DPD) receivers GENERAL DESCRIPTION The ADRF6620 is a highly integrated active mixer and synthesizer that is ideally suited for wireless receiver subsystems. The feature rich device consists of a high linearity broadband active mixer; an integrated fractional-N PLL; low phase noise, multicore VCO; and IF DGA. In addition, the ADRF6620 integrates a 4:1 RF switch, an on-chip tunable RF balun, programmable RF attenuator, and low dropout (LDO) regulators. This highly integrated device fits within a small 7 mm × 7 mm footprint. The high isolation 4:1 RF switch and on-chip tunable RF balun enable the ADRF6620 to support four single-ended 50 Ω terminated RF inputs. A programmable attenuator ensures optimal RF input drive to the high linearity mixer core. The integrated DSA has an attenuation range of 0 dB to 15 dB with a step size of 1 dB. FUNCTIONAL BLOCK DIAGRAM RFIN0 RFIN1 RFIN2 RFIN3 IFOUT1– IFOUT1+ IFOUT2– IFOUT2+ REFIN ÷8 ÷4 ÷2 ×1 ×2 LOIN+ LOIN– PFD CHARGE CP + PUMP VTUNE ÷1, ÷2, ÷4, ÷8 N = INT + FRAC MOD ÷2 LOIN+ LOIN– VTUNE CP MUXOUT LOCK_DET VPTAT LDO 2.5 V SERIAL PORT INTERFACE LDO VCO LDO 3.3V Figure 1. The ADRF6620 offers two alternatives for generating the dif- ferential LO input signal: externally, via a high frequency, low phase noise LO signal, or internally, via the on-chip fractional-N PLL synthesizer. The integrated synthesizer enables continuous LO coverage from 350 MHz to 2850 MHz. The PLL reference input can support a wide frequency range because the divide and multiply blocks can be used to increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (PFD). The integrated high linearity DGA provides an additional gain range from 3 dB to 15 dB in steps of 0.5 dB for maximum flexibility in driving an analog-to-digital converter (ADC). The ADRF6620 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 48-lead, RoHS-compliant, 7 mm × 7 mm LFCSP package with an exposed pad. Performance is specified over the −40°C to +85°C temperature range. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADRF6620 Data Sheet SYNTHESIZER/PLL SPECIFICATIONS VCCx = 5 V, TA = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, and loop filter bandwidth = 120 kHz, unless otherwise noted. Table 3. Parameter PLL REFERENCE PLL Reference Frequency PLL Reference Level PFD FREQUENCY INTERNAL VCO RANGE OPEN-LOOP VCO PHASE NOISE fVCO2 = 3.4 GHz fVCO1 = 4.6 GHz fVCO0 = 5.5 GHz SYNTHESIZER SPECIFICATIONS fLO = 1.710 GHz, fVCO2 = 3.420 GHz fPFD Spurs Closed-Loop Phase Noise Integrated Phase Noise Figure of Merit (FOM)1 Test Conditions/Comments Min Typ Max Unit For PLL lock condition VTUNE = 2 V, LO_DIV_A = 00 1 kHz offset 10 kHz offset 100 kHz offset 800 kHz offset 1 MHz offset 6 MHz offset 10 MHz offset 40 MHz offset VCO sensitivity (KV) 1 kHz offset 10 kHz offset 100 kHz offset 800 kHz offset 1 MHz offset 6 MHz offset 10 MHz offset 40 MHz offset VCO sensitivity (KV) 1 kHz offset 10 kHz offset 100 kHz offset 800 kHz offset 1 MHz offset 6 MHz offset 10 MHz offset 40 MHz offset VCO sensitivity (KV) Measured at LO output, LO_DIV_A = 01 fREF = 153.6 MHz, fPFD = 38.4 MHz, 120 kHz loop filter fPFD × 1 fPFD × 2 fPFD × 3 fPFD × 4 1 kHz offset 10 kHz offset 100 kHz offset 800 kHz offset 1 MHz offset 6 MHz offset 10 MHz offset 40 MHz offset 10 kHz to 40 MHz integration bandwidth 12 −15 24 2800 +4 464 +14 58 5700 MHz dBm MHz MHz −39 −81 −103 −123 −125 −143 −147 −155 88 −39 −74 −101 −123 −125 −143 −147 −156 89 −39 −69 −99 −121 −124 −142 −146 −155 72 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz/V −83 −89 −90 −93 −97 −110 −107 −128 −132 −144 −152 −158 0.21 −222 dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ° rms dBc/Hz Rev. 0 \| Page 4 of 52 5 Page ADRF6620 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Data Sheet VCC1 1 DECL1 2 CP 3 GND 4 GND 5 REFIN 6 DECL2 7 IFOUT1+ 8 IFOUT1– 9 IFOUT2+ 10 IFOUT2– 11 VCC2 12 PIN 1 INDICATOR ADRF6620 TOP VIEW (Not to Scale) 36 GND 35 RFIN0 34 GND 33 GND 32 RFIN1 31 GND 30 GND 29 RFIN2 28 GND 27 GND 26 RFIN3 25 GND NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH LOW THERMAL IMPEDANCE. Figure 3. Pin Configuration Table 9. Pin Function Descriptions1 Pin No. Mnemonic 1, 12, 13, 14, 24 VCC1, VCC2, VCC3, VCC4, VCC5 2, 7, 37, 46 DECL1, DECL2, DECL3, DECL4 3 CP 4, 5, 17, 20, 23, 25, 27, GND 28, 30, 31, 33, 34, 36, 48 6 REFIN 8 to 11 IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2− 15, 16 18, 19 21, 22 26, 29, 32, 35 38, 39 40 41 42 43 44, 45 47 49 IFIN−, IFIN+ MXOUT+, MXOUT− LOOUT+, LOOUT− RFIN3, RFIN2, RFIN1, RFIN0 RFSW0, RFSW1 CS SCLK SDIO MUXOUT LOIN−, LOIN+ VTUNE EPAD Description 5 V Power Supplies. Decouple all power supply pins to ground, using 100 pF and 0.1 µF capacitors. Place the decoupling capacitors near the pins. Decouple all DECLx pins to ground, using 100 pF, 0.1 µF, and 10 µF capacitors. Place the decoupling capacitors near the pins. Synthesizer Charge Pump Output. Connect this pin to the VTUNE pin through the loop filter. Ground. Synthesizer Reference Frequency Input. IF DGA Outputs. Connect the positive pins such that IFOUT1+ and IFOUT2+ are tied together. Similarly, connect the negative pins such that IFOUT1− and IFOUT2− are tied together. Refer to the Layout section for a recommended layout that minimizes parasitic capacitance and optimizes performance. Differential IF DGA Inputs. AC couple the mixer outputs to the IF DGA inputs. Differential Mixer Outputs. AC couple the mixer outputs to the IF DGA inputs. Differential LO Outputs. The differential output impedance is 50 Ω. RF Inputs. These single-ended RF inputs have a 50 Ω input impedance and must be ac-coupled. External Pin Control of RF Input Switches. For logic high, connect these pins to 2.5 V logic. SPI Chip Select, Active Low. 3.3 V tolerant logic levels. SPI Clock. 3.3 V tolerant logic levels. SPI Data Input or Output. 3.3 V tolerant logic levels. Multiplexer Output. This output pin provides the PLL reference signal or the PLL lock detect signal. Differential Local Oscillator Inputs. The differential input impedance is 50 Ω. VCO Tuning Voltage. Connect this pin to the CP pin through the loop filter. Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance. 1 For more connection information about these pins, see Table 14. Rev. 0 \| Page 10 of 52 11 Page

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