ADRF6658 Datasheet PDF - Analog Devices
| Part Number | ADRF6658 | |
| Description | Dual Rx Mixers | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Data Sheet
Wideband, Dual Rx Mixers
with Integrated IF Amplifiers
ADRF6658
FEATURES
GENERAL DESCRIPTION
Wideband, dual-channel, active downconversion mixers
Low distortion, fast settling, IF DGAs
RF input frequency range: 690 MHz to 3.8 GHz
Programmable baluns on RF inputs
For RF = 1950 MHz, IF = 281 MHz, high linearity mode
Voltage conversion gain, including IF filter loss:
−5 dB to +26.5 dB
Input IP3: 29 dBm at minimum DGA gain
Input P1dB: 12 dBm at minimum DGA gain
SSB NF: 13 dB at maximum DGA gain
Output IP3: 40 dBm at maximum DGA gain
Output P1dB: 19 dBm at maximum DGA gain
Channel isolation: 52 dB
Differential and single-ended LO input modes
Differential IF output impedance: 100 Ω
Flexible power-down modes for low power operation
Power-up time after enabling channels: 100 ns, typical
Programmable via a 3-wire serial port interface (SPI)
Single 3.3 V supply
High linearity mode: 440 mA
Low power mode: 260 mA
APPLICATIONS
Cellular base stations and wireless infrastructure receivers
(W-CDMA, TD-SCDMA, WiMAX, GSM, LTE, PCS, DCS, DECT)
Active antenna systems
PTP radio link down converters
Wireless LANs and CATV equipment
The ADRF6658 is a high performance, low power, wideband,
dual-channel radio frequency (RF) downconverter with
integrated intermediate frequency (IF) digitally controlled
amplifiers (DGAs) for wideband, low distortion base station
radio receivers.
The dual Rx mixers are doubly balanced Gilbert cell mixers
with high linearity and excellent image rejection. Both mixers
convert 50 Ω RF inputs to open-collector broadband IF outputs.
Internal tunable baluns on the RF inputs enable suppression of
RF signal harmonics and attenuation of out-of-band signals
before the mixer inputs, reducing input reflections and out-of-
band interference signals. A flexible local oscillator (LO)
architecture allows the use of differential or single-ended LO
signals.
The dual-channel IF DGAs are based on the ADL5201 and
ADL5202 and have a fixed, differential output impedance of
100 Ω. The gain is adjustable over a 31.5 dB range with a 0.5 dB
step size via the on-chip SPI, or through independent, 6-bit
parallel ports that support latch functionality. Each channel,
from the mixer inputs to the IF amplifier outputs, together with
an LC interstage band-pass filter, achieves a maximum voltage
conversion gain of 26.5 dB.
Fabricated with the Analog Devices, Inc., high speed SiGe
process, the ADRF6658 is available in a compact, 7 mm ×
7 mm, 48-lead LFCSP package, and operates over the −40°C to
+105°C temperature range.
LOVDD MIXAVDD
FUNCTIONAL BLOCK DIAGRAM
MIXAOUT+ MIXAOUT– CHAEN DGAAIN– DGAAIN+ LATCHA A0 TO A5
DGAAVDD
DVDD
MIXARFIN
LOIN+
LOIN–
MIXBRFIN
MIXA
MIXB
ADRF6658
LATCH A
0dB TO 31.5dB
0dB TO 31.5dB
LATCH B
+22dB
100Ω
CONTROL
REGISTERS
IFAOUT+
IFAOUT–
SDO
DATA
CLK
LE
+22dB
100Ω
IFBOUT+
IFBOUT–
MIXBVDD
MIXBOUT+ MIXBOUT–
CHBEN DGABIN– DGABIN+
Figure 1.
LATCHB
B0 TO B5
DGABVDD
AGND
Rev. A
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADRF6658
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
DVDD
MIXAVDD, MIXBVDD, DGAAVDD,
DGABVDD, and LOVDD
External IFXOUT± Pull-Up Supply
Mixer Current in High Linearity
Mode
Mixer Current in Low Power Mode
IF DGA Current
Total Current
High Linearity Mode
Low Power Mode
Low Power Sleep Mode
Standby Mode
TIMING2
Channel Power-Up from Standby
Mode After Changing State of
CHAEN or CHBEN
Min
1.17
−0.5
VLOGIC − 0.4
3.15
Typ Max
3.6
+0.63
±1
2
3.3
DVDD
80
40
140
440
260
450
65
100
500
0.4
3.45
DVDD
550
1000
400
1 DC-coupled; lower cutoff frequency determined mostly by external components.
2 Not tested in production; guaranteed by characterization.
Data Sheet
Unit Test Conditions/Comments
V
V
µA
pF
SDO (Pin 32)
V VLOGIC selected with Register 5, Bit DB24
µA
V IOL = 500 µA
V
The voltages on these pins must equal DVDD
V
mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4
mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1
mA Per amplifier
Dual Rx enabled
mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4
mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1
µA
mA Both mixers and DGAs in standby mode
ns From standby mode to normal operation
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