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PDF ADG3233 Data sheet ( Hoja de datos )
| Número de pieza | ADG3233 | |
| Descripción | Bypass Switch | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Voltage 1.65 V to 3.6 V, Bidirectional
Logic Level Translation, Bypass Switch
ADG3233
FEATURES
Operates from 1.65 V to 3.6 V supply rails
Bidirectional level translation, unidirectional signal path
8-lead SOT-23 and MSOP packages
Bypass or normal operation
Short circuit protection
APPLICATIONS
JTAG chain bypassing
Daisy-chain bypassing
Digital switching
FUNCTIONAL BLOCK DIAGRAM
VCC1 VCC2
VCC1
A1 Y1
VCC1
A2
VCC1 VCC2
VCC2
0
1
Y2
GENERAL DESCRIPTION
The ADG32331 is a bypass switch designed on a submicron
process that operates from supplies as low as 1.65 V. The device
is guaranteed for operation over the supply range 1.65 V to 3.6 V. It
operates from two supply voltages, allowing bidirectional level
translation, that is, it translates low voltages to higher voltages
and vice versa. The signal path is unidirectional, meaning data
may only flow from A → Y.
This type of device may be used in applications that require a
bypassing function. It is ideally suited to bypassing devices in
a JTAG chain or in a daisy-chain loop. One switch could be
used for each device or a number of devices, thus allowing
easy bypassing of one or more devices in a chain. This may
be particularly useful in reducing the time overhead in testing
devices in the JTAG chain or in daisy-chain applications where
the user does not wish to change the settings of a particular device.
The bypass switch is packaged in two of the smallest footprints
available for its required pin count. The 8-lead SOT-23 package
requires only 2.9 mm × 2.8 mm board space, while the MSOP
package occupies approximately 3 mm × 4.9 mm board area.
EN ADG3233
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Bidirectional level translation matches any voltage level
from 1.65 V to 3.6 V.
2. The bypass switch offers high performance and is fully
guaranteed across the supply range.
3. Short circuit protection.
4. Tiny 8-lead SOT-23 package and 8-lead MSOP.
Table 1. Truth Table
EN Signal Path
L A1 → Y2, Y1 → VCC1
H A1 → Y1, A2 → Y2
Function
Enable bypass mode
Enable normal mode
1 U.S. Patent Number: 7,369,385 B2.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADG3233
Data Sheet
Parameter1
VCC = VCC1 = VCC2 = 2.5 V ± 0.2 V
Propagation Delay, tPD
A1 → Y1 Normal Mode
A2 → Y2 Normal Mode
A1 → Y2 Bypass Mode
ENABLE Time EN → Y1
DISABLE Time EN → Y1
ENABLE Time EN → Y2
DISABLE Time EN → Y2
VCC = VCC1 = VCC2 = 1.8 V ± 0.15 V
Propagation Delay, tPD
A1 → Y1 Normal Mode
A2 → Y2 Normal Mode
A1 → Y2 Bypass Mode
ENABLE Time EN → Y1
DISABLE Time EN → Y1
ENABLE Time EN → Y2
DISABLE Time EN → Y2
Input Leakage Current
Output Leakage Current
POWER REQUIREMENTS
Power Supply Voltages
Quiescent Power Supply Current
Increase in ICC per Input
Symbol Test Conditions/Comments
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tEN
tDIS
tEN
tDIS
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tEN
tDIS
tEN
tDIS
II
IO
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
CL = 30 pF, VT = VCC/2
0 ≤ VIN ≤ 3.6 V
0 ≤ VIN ≤ 3.6 V
VCC1
VCC2
ICC1
ICC2
ΔICC1
Digital inputs = 0 V or VCC
Digital inputs = 0 V or VCC
VCC = 3.6 V, one input at 3.0 V; others at
VCC or GND
Min
1.65
1.65
Typ2 Max
Unit
4.5 6.2
4.5 6.2
4.5 6.5
5 7.2
3.2 4.7
5 7.7
4.8 7.2
ns
ns
ns
ns
ns
ns
ns
6.7 10
6.5 10
6.5 10.25
7 10.5
4.4 6.5
7 12
6.5 10.5
±1
±1
3.6
3.6
2
2
0.75
ns
ns
ns
ns
ns
ns
ns
µA
µA
V
V
µA
µA
µA
1 Temperature range is as follows: B Version: −40°C to +85°C.
2 All typical values are at VCC = VCC1 = VCC2, TA = 25°C, unless otherwise stated.
3 VIL and VIH levels are specified with respect to VCC1, VOH, and VOL levels for Y1 are specified with respect to VCC1, and VOH, and VOL levels are specified for Y2 with respect to
VCC2.
4 Guaranteed by design, not subject to production test.
5 See the Test Waveforms section.
Rev. C | Page 4 of 16
5 Page 
ADG3233
16
VCC1 = 3.3V
14
VCC2 = 1.8V
TA = 25°C
DATA RATE = 10Mbps
12
10
8
tPLH, LOW-TO-HIGH TRANSITION
6
4
2 tPHL, HIGH-TO-LOW TRANSITION
0
22 32 42 52 62 72 82 92 102
CAPACITIVE LOAD (pF)
Figure 19. Rise/Fall Time vs. Capacitive Load, A1 → Y1, A2 → Y2
16
VCC1 = 3.3V
14
VCC2 = 1.8V
TA = 25°C
DATA RATE = 10Mbps
12
10
tPLH, LOW-TO-HIGH TRANSITION
8
6
4
2 tPHL, HIGH-TO-LOW TRANSITION
0
22 32 42 52 62 72 82 92 102
CAPACITIVE LOAD (pF)
Figure 20. Rise/Fall Time vs. Capacitive Load, A1 → Y2, Bypass Mode
10
VCC1 = 1.8V
9 VCC2 = 3.3V
TA = 25°C
8 DATA RATE = 10Mbps
7
6 tPLH, LOW-TO-HIGH TRANSITION
5
4
3
tPHL, HIGH-TO-LOW TRANSITION
2
1
0
22 32 42 52 62 72 82 92 102
CAPACITIVE LOAD (pF)
Figure 21. Rise/Fall Time vs. Capacitive Load, A1 → Y1, A2 → Y2
Data Sheet
10
VCC1 = 1.8V
9 VCC2 = 3.3V
TA = 25°C
8 DATA RATE = 10Mbps
7
6 tPLH, LOW-TO-HIGH TRANSITION
5
4
3
tPHL, HIGH-TO-LOW TRANSITION
2
1
0
22 32 42 52 62 72 82 92 102
CAPACITIVE LOAD (pF)
Figure 22. Rise/Fall Time vs. Capacitive Load, A1 → Y2, Bypass Mode
8
VCC1 = 3.3V
7
VCC2 = 3.3V
TA = 25°C
DATA RATE = 10Mbps
6
tPLH, LOW-TO-HIGH TRANSITION
5
4
tPHL, HIGH-TO-LOW TRANSITION
3
2
1
0
22 32 42 52 62 72 82 92 102
CAPACITIVE LOAD (pF)
Figure 23. Propagation Delay vs. Capacitive Load A1 → Y1
8
7
tPLH, LOW-TO-HIGH TRANSITION
6
5
tPHL, HIGH-TO-LOW TRANSITION
4
3
2
VCC1 = 3.3V
1
VCC2 = 3.3V
TA = 25°C
DATA RATE = 10Mbps
0
22 32 42 52 62 72
CAPACITIVE LOAD (pF)
82
92 102
Figure 24. Propagation Delay vs. Capacitive Load A2 → Y2
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADG3233.PDF ] | |
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