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ADN4612 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN4612
Beschreibung 12 x 12 Digital Crosspoint Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADN4612 Datasheet, Funktion
Data Sheet
FEATURES
DC to 11.3 Gbps per port, NRZ data rate
Multitime constant, programmable receive equalization
Compensates 25 inches of FR408 at 10.3125 Gbps
Compensates 15 inches of FR408 at 11.3 Gbps
6-tap programmable transmit feedforward equalization (FFE)
Compensates 15 inches of FR408 at 10.3125 Gbps
Compensates 10 inches of FR408 at 11.3 Gbps
Low power
150 mW per channel at 2.5 V (outputs enabled)
12 × 12, fully differential, nonblocking array
Double rank connection programming
2-pin selectable connection maps
Per lane lost of signal (LOS) detection
Flexible output termination supply range (1.8 V to 3.3 V)
DC- or ac-coupled differential CML inputs and outputs
Programmable CML output levels
Load from EEPROM for automatic power-on ready operation
Per lane input and output P/N pair inversion for routing ease
50 Ω on-chip input/output termination
Supports 64-bit/66-bit, scrambled or not coded NRZ data up
to 11.3 Gbps
Serial (I2C or SPI slave) control interface
88-lead LFCSP, 12 mm × 12 mm, Pb-free package
−40°C to +85°C operating temperature range
APPLICATIONS
Fiber optic network switching
10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap
XLAUI/CAUI (802.3ba)
SONET OC-192/STM-64x
1×, 2×, 4×, 8×, and 10× Fibre Channel
GENERAL DESCRIPTION
The ADN4612 is a 12 × 12 asynchronous, protocol agnostic, digital
crosspoint switch with 12 differential PECL-/CML-compatible
inputs and 12 differential CML outputs.
The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling
with data rates of up to 11.3 Gbps per port. Each port provides
programmable input equalization, loss of signal (LOS) detection,
programmable output swing, and output preemphasis/deemphasis.
11.3 Gbps, 12 × 12 Digital
Crosspoint Switch
ADN4612
FUNCTIONAL BLOCK DIAGRAM
DVCC
VCC
IP11
TO IP0
Rx
Tx
OP11
TO OP0
VTTIE,
VTTIW
12 × 12
SWITCH
MATRIX
PRE-
EMPHASIS
VTTON,
VTTOS
IN11
EQ
ON11
TO IN0
TO ON0
Rx CONTROL
EQUALIZATION
SIGNAL DETECT
XPT CONTROL
CONNECTIVITY
MAP (A/B/C/D)
SELECT
Tx CONTROL
6-TAP FFE
OUTPUT LEVEL
EEPROM
MAP1, MAP0
RESET
UPDATE
SPI/I2C
SCK/SCL
SDO/SDA
SDI/I2C_A1
CS/I2C_A0
LOS_IRQ
SERIAL
INTERFACE
CONTROL
LOGIC
ADN4612
VEE
Figure 1.
The ADN4612 nonblocking switch core implements a 12 × 12
crossbar and supports independent channel switching through
the serial control interface. The ADN4612 has low latency and
very low channel-to-channel skew.
The ADN4612 is packaged in an 88-lead LFCSP package and
operates from −40°C to +85°C.
Rev. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADN4612 Datasheet, Funktion
Data Sheet
ADN4612
POWER SUPPLY AND THERMAL SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min Typ Max Unit
POWER SUPPLY OPERATING RANGE VEE = 0 V
VCC 2.25 2.5 2.75 V
DVCC
1.6 1.8 2.0 V
VCC1P8
1.6 1.8 2.0 V
VTTI1 1.6 1.8 2.752 V
VTTO3
1.64 2.5 3.6 V
POWER SUPPLY NOISE TOLERANCE
VCC 10 Hz to 6.25 GHz
100 mV p-p
DVCC
10 Hz to 100 MHz
100 mV p-p
VCC1P8
10 Hz to 100 MHz
25 mV p-p
VTTI1 10 Hz to 6.25 GHz
100 mV p-p
VTTO3
10 Hz to 6.25 GHz
100 mV p-p
SUPPLY CURRENT
ICC
VCC = 2.5 V
Default, all outputs disabled
120 140 mA
All outputs and main tap enabled, single driver (D0) enabled
391 430 mA
All outputs and main tap enabled, two drivers (D0, D1) enabled
537 590 mA
All outputs and main tap enabled, three drivers (D0 to D2) enabled
684 760 mA
All outputs and main tap and first post tap (D0 to D3) enabled
829 920 mA
All outputs, precursor, main tap, and first post tap (PC, D0 to D3) enabled
944 1070 mA
ITTO5
VTTO = 2.5 V
Default, all outputs disabled
0 <1 mA
All outputs enabled, 8 mA output current per lane
96 106 mA
All outputs enabled, 16 mA output current per lane
192 206 mA
All outputs enabled, 24 mA output current per lane
287 314 mA
All outputs enabled, 32 mA output current per lane
384 416 mA
ITTI6 0 mA
IDVCC
8 12 mA
IVCC1P8
Default, all outputs disabled
78
mA
All outputs main tap enabled
40 43
mA
THERMAL CHARACTERISTICS
Operating Temperature Range
−40 +85 °C
θJA
Still air; JEDEC 4-layer test board, exposed pad soldered
24.0 °C/W
θJC
Still air; thermal resistance through exposed pad
1.7 °C/W
Maximum Junction Temperature
125 °C
1 VTTI is a generic variable that describes both VTTIE and VTTIW. VTTIE and VTTIW are independent voltages that are not required to equal each other.
2 It is recommended that VTTI ≤ VCC to meet the input compliance.
3 VTTO is a generic variable that describes both VTTON and VTTOS. VTTON and VTTOS are independent voltages that are not required to equal each other.
4 The single-ended absolute voltage level, VOL, must be ≤VCC − 1.2 V when operating VTTO at the minimum boundary of the supply range.
5 ITTO is a generic variable that describes both ITTON and ITTOS. ITTON and ITTOS are independent currents that are not required to equal each other.
6 ITTI is a generic variable that describes both ITTIE and ITTIW. ITTIE and ITTIW are independent currents that are not required to equal each other.
Rev. C | Page 5 of 76

6 Page









ADN4612 pdf, datenblatt
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IP0 1
IN0 2
VEE 3
IP1 4
IN1 5
VCC 6
IP2 7
IN2 8
VTTIW 9
IP3 10
IN3 11
VCC 12
IP4 13
IN4 14
VEE 15
IP5 16
IN5 17
VTTIW 18
EEPROM 19
LOS_IRQ 20
MAP0 21
MAP1 22
ADN4612
TOP VIEW
(Not to Scale)
66 SDI/I2C_A1
65 CS/I2C_A0
64 VTTIE
63 IN11
62 IP11
61 VEE
60 IN10
59 IP10
58 VCC
57 IN9
56 IP9
55 VTTIE
54 IN8
53 IP8
52 VCC
51 IN7
50 IP7
49 VEE
48 IN6
47 IP6
46 RESET
45 SPI/I2C
ADN4612
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE ELECTRICALLY CONNECTED TO VEE.
Figure 6. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
6, 12, 29, 35, 42, 52, 58, 75, 81 VCC
88 VCC1P8
68 DVCC
3, 15, 26, 32, 38, 49, 61, 72, 78, 84 VEE
9, 18 VTTIW
55, 64
VTTIE
69, 87
VTTON
23, 41
VTTOS
19 EEPROM
20 LOS_IRQ
21 MAP0
22 MAP1
43 SCK/SCL
44 SDO/SDA
45 SPI/I2C
46 RESET
65 CS/I2C_A0
66 SDI/I2C_A1
67 UPDATE
1 IP0
2 IN0
4 IP1
5 IN1
7 IP2
8 IN2
10 IP3
11 IN3
Type
Power
Power
Power
Power
Power
Power
Power
Power
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
I
I
I
I
I
I
I
I
Description
Core Power Supplies.
Analog 1.8 V Reference Supply.
Digital Power Supply.
Negative Supplies.
Westside Input Termination Supplies.
Eastside Input Termination Supplies.
Northside Output Termination Supplies.
Southside Output Termination Supplies.
Load from EEPROM (Active Low).
Loss of Signal Detect Interrupt Request Output (Active Low).
Map Select LSB.
Map Select MSB.
SPI Serial Clock (SCK)/I2C Serial Clock (SCL). This is a multifunction pin.
SPI Serial Data Output (SDO)/I2C Serial Data (SDA). This is a multifunction pin.
SPI Mode Select (SPI)/I2C Mode Select (I2C). This is a multifunction pin.
Reset (Active Low).
SPI Chip Select, Active Low (CS)/I2C Address LSB (I2C_A0). This is a multifunction pin.
SPI Serial Data Input (SDI)/I2C Address MSB (I2C_A1). This is a multifunction pin.
Switch Configuration Update Strobe (Active Low).
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
Rev. C | Page 11 of 76

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