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PDF AD7791 Data sheet ( Hoja de datos )
| Número de pieza | AD7791 | |
| Descripción | Buffered 24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 μA max
Power-down: 1 μA max
RMS noise: 1.1 μV at 9.5 Hz update rate
19.5-bit p-p resolution (22 bits effective resolution)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Rail-to-rail input buffer
VDD monitor channel
Temperature range: –40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Low Power, Buffered 24-Bit
Sigma-Delta ADC
AD7791
FUNCTIONAL BLOCK DIAGRAM
GND VDD REFIN(+) REFIN(–)
VDD
CLOCK
AIN(+)
AIN(–)
GND
BUF
-
ADC
AD7791
Figure 1.
SERIAL
INTERFACE
DOUT/RDY
DIN
SCLK
CS
04227-0-001
GENERAL DESCRIPTION
The AD7791 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 24-bit ∑-Δ ADC with one differential input that can be
buffered or unbuffered.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 μV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc-
tion in the current consumption. The update rate, cutoff fre-
frequency, and settling time will scale with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 μW maximum. It is housed in a 10-lead MSOP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7791
Data Sheet
SPECIFICATIONS (continued)1
Parameter
REFERENCE INPUT (continued)
Normal Mode Rejection2
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common Mode Rejection
@ DC
@ 50 Hz, 60 Hz
LOGIC INPUTS
All Inputs Except SCLK2
VINL, Input Low Voltage
VINH, Input High Voltage
SCLK Only (Schmitt-Triggered Input)2
VT(+)
VT(–)
VT(+) – VT(–)
VT(+)
VT(–)
VT(+) - VT(–)
Input Currents
Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage2
VOL, Output Low Voltage2
VOH, Output High Voltage2
VOL, Output Low Voltage2
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
POWER REQUIREMENTS5
Power Supply Voltage
VDD – GND
Power Supply Currents
IDD Current6
IDD (Power-Down Mode)
AD7791B
65
80
80
100
110
0.8
0.4
2.0
1.4/2
0.8/1.4
0.3/0.85
0.9/2
0.4/1.1
0.3/0.85
±1
10
VDD – 0.6
0.4
4
0.4
±1
10
Offset Binary
2.5/5.25
75
145
80
160
1
Unit
dB min
dB min
dB min
dB typ
dB typ
V max
V max
V min
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
µA max
pF typ
V min
V max
V min
V max
µA max
pF typ
V min/max
µA max
µA max
µA max
µA max
µA max
Test Conditions/Comments
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114
AIN = 1 V
FS[2:0] = 1004
50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)
VDD = 5 V
VDD = 3 V
VDD = 3 V or 5 V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VDD = 3 V
VIN = VDD or GND
All Digital Inputs
VDD = 3 V, ISOURCE = 100 µA
VDD = 3 V, ISINK = 100 µA
VDD = 5 V, ISOURCE = 200 µA
VDD = 5 V, ISINK = 1.6 mA
65 µA typ, VDD = 3.6 V, Unbuffered Mode
130 µA typ, VDD = 3.6 V, Buffered Mode
73 µA typ, VDD = 5.25 V, Unbuffered Mode
145 µA typ, VDD = 5.25 V, Buffered Mode
5 Digital inputs equal to VDD or GND.
6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).
Rev. A | Page 4 of 20
5 Page 
AD7791
Data Sheet
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the
communications register. The data written to the communications register determines whether the next operation is a read or write oper-
ation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the
selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default
state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communica-
tions register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns
the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0
through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data
stream. The number in brackets indicates the power-on/reset default status of that bit.
CR7
WEN(0)
CR6
0(0)
CR5
RS1(0)
CR4
RS0(0)
CR3
R/W(0)
CR2
CREAD(0)
CR1
CH1(0)
CR0
CH0(0)
Table 5. Communications Register Bit Designations
Bit Location Bit Name
Description
CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6 0
This bit must be programmed to Logic 0 for correct operation.
CR5–CR4
RS1–RS0
Register Address Bits. These address bits are used to select which of the ADC’s registers are being select-
ed during this serial interface communication. See Table 6.
CR3 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR2
CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
CR1–CR0
CH1–CH0
These bits are used to select the analog input channel. The differential channel can be selected
(AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to digi-
tal conversion. Any change in channel resets the filter and a new conversion is started.
Table 6. Register Selection
RS1 RS0
Register
00
Communications Register
during a Write Operation
00
Status Register during a
Read Operation
01
Mode Register
10
Filter Register
11
Data Register
Register Size
8-Bit
8-Bit
8-Bit
8-Bit
24-Bit
Table 7. Channel Selection
CH1 CH0 Channel
0 0 AIN(+) – AIN(–)
0 1 Reserved
1 0 AIN(–) – AIN(–)
1 1 VDD Monitor
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7791.PDF ] | |
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