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AD7656A-1 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7656A-1
Beschreibung 16-Bit ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD7656A-1 Datasheet, Funktion
Data Sheet
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar, 16-Bit ADC
AD7656A-1
FEATURES
Pin and software compatible with the AD7656A featuring
reduced decoupling requirements
6 independent analog-to-digital converters (ADCs)
True bipolar analog inputs
Pin-/software-selectable ranges: ±10 V or ±5 V
Fast throughput rate: 250 kSPS
iCMOS process technology
Low power: 140 mW at 250 kSPS with 5 V supplies
High noise performance with wide bandwidth
88 dB SNR at 10 kHz input frequency
On-chip reference and reference buffers
High speed parallel, serial, and daisy-chain interface modes
High speed serial interface
Serial peripheral interface (SPI)/QSPI™/MICROWIRE®/DSP
compatible
Power-down mode: 315 µW maximum
64-lead LQFP
Built-in power supply sequencing (PSS) robustness solution
APPLICATIONS
Power line monitoring and measuring systems
Instrumentation and control systems
Multiaxis positioning systems
FUNCTIONAL BLOCK DIAGRAM
VDD CONVST A CONVST B CONVST C AVCC DVCC
REF
CLK
OSC
CONTROL
LOGIC
V1 T/H
BUF
16-BIT SAR
OUTPUT
DRIVERS
V2 T/H
V3 T/H
BUF
16-BIT SAR
16-BIT SAR
V4 T/H
V5 T/H
BUF
16-BIT SAR
16-BIT SAR
OUTPUT
DRIVERS
OUTPUT
DRIVERS
OUTPUT
DRIVERS
V6 T/H
VSS
16-BIT SAR
AD7656A-1
AGND DGND
Figure 1.
CS
SER/PAR SEL
VDRIVE
STBY
DB8/DOUT A
DB6/SCLK
DB9/DOUT B
DB10/DOUT C
DATA/
CONTROL
LINES
RD
WR/REFEN/DIS
GENERAL DESCRIPTION
The AD7656A-11 is a reduced decoupling pin- and software-
compatible version of AD7656A. The AD7656A-1 contains six
16-bit, fast, low power successive approximation ADCs in a
package designed on the iCMOS® process (industrial CMOS).
iCMOS is a process combining high voltage silicon with submicron
CMOS and complementary bipolar technologies. It enables the
development of a wide range of high performance analog ICs,
capable of 33 V operation in a footprint that no previous
generation of high voltage devices could achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can accept bipolar input signals while providing increased
performance, which dramatically reduces power consumption
and package size.
The AD7656A-1 features throughput rates of to 250 kSPS. It
contains wide bandwidth (4.5 MHz), track-and-hold amplifiers
that can handle input frequencies up to 4.5 MHz.
1 Protected by U.S. Patent No. 6,731,232.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
The conversion process and data acquisition are controlled
using the CONVST x signals and an internal oscillator. Three
CONVST x pins (CONVST A, CONVST B, and CONVST C)
allow independent, simultaneous sampling of the three ADC
pairs. The AD7656A-1 has a high speed parallel and serial
interface, allowing the device to interface with microprocessors
or digital signal processors (DSPs). In serial interface mode, the
AD7656A-1 has a daisy-chain feature that allows multiple
ADCs to connect to a single serial interface. The AD7656A-1
can accommodate true bipolar input signals in the ±4 × VREF
range and the ±2 × VREF range. The AD7656A-1 also contains
an on-chip 2.5 V reference.
Multifunction pin names may be referenced by their relevant
function only.
PRODUCT HIGHLIGHTS
1. Six 16-bit, 250 kSPS ADCs on board.
2. Six true bipolar, high impedance analog inputs.
3. High speed parallel and serial interfaces.
4. Reduced decoupling requirements and reduced bill of
materials cost compared with the AD7656A.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD7656A-1 Datasheet, Funktion
Data Sheet
AD7656A-1
TIMING SPECIFICATIONS
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the
±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to
−16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V.
Table 2.
Parameter
PARALLEL INTERFACE MODE
tCONV
tQUIET
tACQ
t10
t1
tWAKE-UP
PARALLEL READ OPERATION
t2
t3
t4
t5
t6
t7
t8
t9
PARALLEL WRITE OPERATION
t11
t12
t13
t14
t15
SERIAL INTERFACE MODE
fSCLK
t16
t172
t18
t19
t20
t21
Limit at TMIN, TMAX
VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V
33
150 150
550 550
25 25
60 60
22
25 25
00
00
00
45 36
45 36
10 10
12 12
66
15 15
00
55
55
55
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
Unit
Description1
µs typ
ns min
ns min
ns min
ns max
ms max
µs max
Conversion time, internal clock
Minimum quiet time required between bus
relinquish and start of next conversion
Acquisition time
Minimum CONVST x low pulse
CONVST x high to BUSY high
STBY rising edge to CONVST x rising edge, not
shown in figures
Partial power-down mode
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
ns min
ns min
ns min
ns min
ns min
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
Frequency of serial read clock
Delay from CS until DOUT x three-state disabled
Data access time after SCLK rising edge/CS
falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to DOUT x high impedance
1 Multifunction pin names may be referenced by their relevant function only.
2 A buffer is used on the DOUT x pins (Pin 5 to Pin 7) for this measurement.
200µA
IOL
TO OUTPUT
PIN CL
25pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 28

6 Page









AD7656A-1 pdf, datenblatt
Data Sheet
–80
VDD/VSS = ±16.5V
AVCC/DVCC/VDRIVE = 5.25V
TA = 25°C
INTERNAL REFERENCE
–90 ±4 × VREF RANGE
RSOURCE = 1000Ω
–100
RSOURCE = 220Ω
RSOURCE = 50Ω
–110
RSOURCE = 10Ω
RSOURCE = 100Ω
–120
10
100
ANALOG INPUT FREQUENCY (kHz)
Figure 10. THD vs. Analog Input Frequency for Various Source Impedances,
±4 × VREF Range
–80
VDD/VSS = ±12V
AVCC/DVCC/VDRIVE = 5V
–85 TA = 25°C
INTERNAL REFERENCE
±2 × VREF RANGE
–90
–95 RSOURCE = 1000Ω
–100
–105
–110
RSOURCE = 220Ω
RSOURCE = 100Ω
RSOURCE = 50Ω
RSOURCE = 10Ω
–115
10
100
ANALOG INPUT FREQUENCY (kHz)
Figure 11. THD vs. Analog Input Frequency for Various Source Impedances,
±2 × VREF Range
2.510
AVCC/DVCC/VDRIVE = 5V
2.508 VDD/VSS = ±12V
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
–55 –35 –15
5
25 45 65 85 105
TEMPERATURE (°C)
Figure 12. Reference Voltage vs. Temperature
125
AD7656A-1
3.20
3.15
AVCC/DVCC/VDRIVE = 5V
VDD/VSS = ±12V
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
–55
–35 –15 5 25 45 65 85 105
TEMPERATURE (°C)
Figure 13. Conversion Time vs. Temperature
125
3500
3000
2500
2806
3212
VDD/VSS = ±15V
AVCC/DVCC/VDRIVE = 5V
INTERNAL REFERENCE
8192 SAMPLES
2000
1500
1532
1000
500
0
0
–5
392
57
168
–4 –3 –2 –1
0
1
CODE
Figure 14. Histogram of Codes
25
2
0
3
100
fSAMPLE = 250kSPS
±2 × VREF RANGE
INTERNAL REFERENCE
90 TA = 25°C
fIN = 10kHz
100nF ON VDD AND VSS
80
70
VSS
60
VDD
50
40
30 80 130 180 230 280 330 380 430 480 530
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 15. PSRR vs. Supply Ripple Frequency
Rev. 0 | Page 11 of 28

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