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AD7770 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7770
Beschreibung Simultaneous Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7770 Datasheet, Funktion
Data Sheet
FEATURES
8-channel, 24-bit simultaneous sampling analog-to-digital
converter (ADC)
Single-ended or true differential inputs
Programmable gain amplifier (PGA) per channel (gains of
1, 2, 4, and 8)
Low dc input current: ±8 nA
Up to 32 kSPS output data rate (ODR) per channel
Programmable ODRs and bandwidth
Sample rate converter (SRC) for coherent sampling
Sampling rate resolution up to 15.2 × 10−6 SPS
Low latency sinc3 filter path
Adjustable phase synchronization
Internal 2.5 V reference
Two power modes
High resolution mode
Low power mode
Optimizes power dissipation and performance
Low resolution successive approximation register (SAR) ADC
for system and chip diagnostics
Power supply
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
Digital input/output (I/O) supply: 1.8 V to 3.6 V
Performance temperature range: −40°C to +105°C
Functional temperature range: −40°C to +125°C
Performance
Combined ac and dc performance
103 dB dynamic range at 32 kSPS in high resolution mode
−109 dB total harmonic distortion (THD)
±9 ppm of FSR integral nonlinearity (INL)
±15 µV offset error
±0.1% FS gain error
±10 ppm/°C typical temperature coefficient
APPLICATIONS
Protection relays
General-purpose data acquisition
Industrial process control
GENERAL DESCRIPTION
The AD7770 is an 8-channel, simultaneous sampling ADC. Eight
full sigma-delta (Σ-Δ) ADCs are on chip. The AD7770 provides
a low input current to allow direct sensor connection. Each input
channel has a programmable gain stage allowing gains of 1, 2, 4,
and 8 to map lower amplitude sensor outputs into the full-scale
ADC input range, maximizing the dynamic range of the signal
chain. The AD7770 accepts a VREF voltage from 1 V up to 3.6 V.
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
8-Channel, 24-Bit,
Simultaneous Sampling ADC
AD7770
The analog inputs accept unipolar (0 V to VREF) or true bipolar
(±VREF/2) analog input signals with 3.3 V or ±1.65 V analog
supply voltages, respectively for PGAGAIN = 1. The analog inputs
can accept true differential, pseudo differential, or single-ended
signals to match different sensor output configurations.
Each channel contains a PGA, an ADC modulator and a
sinc3, low latency digital filter. An SRC is provided to allow fine
resolution control over the AD7770 ODR. This control can be
used in applications where the ODR resolution is required to
maintain coherency with 0.01 Hz changes in the line frequency.
The SRC is programmable through the serial port interface (SPI).
The AD7770 implements two different interfaces: a data output
interface and SPI control interface. The ADC data output interface
is dedicated to transmitting the ADC conversion results from
the AD7770 to the processor. The SPI writes to and reads from
the AD7770 configuration registers and for the control and
reading of data from the SAR ADC. The SPI can also be
configured to output the Σ-Δ conversion data.
The AD7770 includes a 12-bit SAR ADC. This ADC can be
used for AD7770 diagnostics without having to decommission
one of the Σ-Δ ADC channels dedicated to system measurement
functions. With the use of an external multiplexer, which can be
controlled through the three general-purpose input/output pins
(GPIOs), and signal conditioning, the SAR ADC can validate
the Σ-Δ ADC measurements in applications where functional
safety is required. In addition, the AD7770 SAR ADC includes
an internal multiplexer to sense internal nodes.
The AD7770 contains a 2.5 V reference and reference buffer. The
reference has a typical temperature coefficient of 10 ppm/°C.
The AD7770 offers two modes of operation: high resolution mode
and low power mode. High resolution mode provides a higher
dynamic range while consuming 10.75 mW per channel; low
power mode consumes just 3.37 mW per channel at a reduced
dynamic range specification.
The specified operating temperature range is −40°C to +105°C,
although the device is operational up to +125°C.
Note that throughout this data sheet, certain terms are used to
refer to either the multifunction pins or a range of pins. The multi-
function pins, such as DCLK0/SDO, are referred to either by the
entire pin name or by a single function of the pin, for example,
DCLK0, when only that function is relevant. In the case of ranges
of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B,
AVSS2A, AVSS2B, AVSS3, and AVSS4.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD7770 Datasheet, Funktion
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD1x REF_OUT REFx+ REFx–
AVDD2 AREGxCAP IOVDD DREGCAP
VCM
AIN0+
AIN0–
AIN1+
AIN1–
AIN2+
AIN2–
AIN3+
AIN3–
AIN4+
AIN4–
AIN5+
AIN5–
AIN6+
AIN6–
AIN7+
AIN7–
AUXAIN+
AUXAIN–
COMMON-
MODE
VOLTAGE
2.5V REF
280mV p-p
EXT_REF
INT_REF
REFERENCES
REFERENCES
REFERENCES
REFERENCES
REFERENCES
REFERENCES
REFERENCES
PGA
PGA
PGA
PGA
PGA
PGA
PGA
PGA
DIAGNOSTIC
INPUTS
ANALOG
LDO
DIGITAL
LDO
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
REGISTER MAP
AND
LOGIC CONTROL
SAR ADC
AVSSx
AVDD4
CONVST_SAR
Figure 1.
AD7770
CLOCK
MANAGER
DATA OUTPUT
INTERFACE
HARDWARE
MODE
CONFIGURATION
XTAL1
XTAL2/MCLK
SYNC_IN
SYNC_OUT
START
DCLK
DRDY
DOUT3
DOUT2
DOUT1
DOUT0
RESET
FORMAT1
FORMAT0
MODE3/ALERT
MODE2/GPIO2
MODE1/GPIO1
MODE0/GPIO0
SPI INTERFACE
ALERT/CS
DCLK2/SCLK
DCLK1/SDI
DCLK0/SDO
AD7770
Rev. B | Page 5 of 97

6 Page









AD7770 pdf, datenblatt
Data Sheet
AD7770
SPI TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,
unless otherwise noted.
Table 3.
Parameter
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22A
t22B
t23
t24
t25
Description2
SCLK period
SCLK low time
SCLK high time
SCLK rising edge to CS falling edge
CS falling edge to SCLK rising edge
SCLK rising edge to CS rising edge
CS rising edge to SCLK rising edge
Minimum CS high time
SDI setup time
SDI hold time
CS falling edge to SDO enable (SPI = Mode 0)
SCLK falling edge to SDO enable (SPI = Mode 1)
SDO setup time
SDO hold time
CS rising edge to SDO disable
Test Conditions/Comments
50:50
Min Typ Max Unit
30 MHz
7 ns
7 ns
10 ns
10 ns
10 ns
10 ns
10 ns
5 ns
5 ns
30 ns
49 ns
10 ns
10 ns
30 ns
1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
t19
CS
t15 t16
SCLK
t13
t14
t17
t20 t12
t18
SDI
MSB MSB – 1
LSB + 1 LSB
t22A
t21
SDO
MSB MSB – 1
LSB + 1
LSB
t22B
t24
t25
t23
Figure 3. SPI Control Interface Timing Diagram
Rev. B | Page 11 of 97

12 Page





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