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ADAU1361 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAU1361
Beschreibung 24-Bit Audio Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADAU1361 Datasheet, Funktion
Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1361
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 1.8 V to 3.65 V
I2C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
Software power-down
32-lead, 5 mm × 5 mm LFCSP
−40°C to +85°C operating temperature range
APPLICATIONS
Smartphones/multimedia phones
Digital still cameras/digital video cameras
Portable media players/portable audio players
Phone accessories products
The ADAU1361 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 14 mW from a 1.8 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control. The
ADAU1361 is ideal for battery-powered audio and telephony
applications.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1361 includes a stereo digital microphone input.
The ADAU1361 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I2C and SPI protocols. The
serial audio bus is programmable for I2S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
FUNCTIONAL BLOCK DIAGRAM
JACKDET/MICIN
HP JACK REGULATOR
DETECTION
ADAU1361
LAUX
LINP
LINN
RINP
RINN
RAUX
INPUT
MIXERS
ALC
ADC
ADC
ADC
DAC
DIGITAL DIGITAL
FILTERS FILTERS
DAC
DAC
OUTPUT
MIXERS
LOUTP
LOUTN
LHP
MONOOUT
RHP
ROUTP
ROUTN
MICBIAS
MICROPHONE
BIAS
PLL
SERIAL DATA
INPUT/OUTPUT PORTS
I2C/SPI
CONTROL PORT
MCLK ADC_SDATA
DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
CLATCH CDATA CCLK COUT
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.






ADAU1361 Datasheet, Funktion
Parameter
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
FULL DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Test Conditions/Comments
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Differential PGA inputs
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
ADAU1361
Min Typ Max Unit
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
92 dB
98 dB
90 dB
95 dB
−88 dB
−89 dB
92 dB
98 dB
90 dB
95 dB
0.75 dB
−12
+35.25
dB
20 dB
−87 dB
0.005
dB
0 mV
−14 %
83 dB
65 dB
65 dB
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
92 dB
98 dB
90 dB
95 dB
−70 dB
−78 dB
92 dB
98 dB
90 dB
95 dB
0.75 dB
−12
+35.25
dB
20 dB
−87 dB
0.005
dB
0 mV
−14 %
Rev. C | Page 5 of 80

6 Page









ADAU1361 pdf, datenblatt
ADAU1361
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V ± 10%.
Table 7. Digital Timing
Parameter
MASTER CLOCK
tMP
tMP
tMP
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
DIGITAL MICROPHONE
tDCF
tDCR
tDDV
tDDH
Limit
tMIN
tMAX
Unit Description
74 488 ns
37 244 ns
24.7
162.7
ns
18.5 122 ns
MCLK period, 256 × fS mode.
MCLK period, 512 × fS mode.
MCLK period, 768 × fS mode.
MCLK period, 1024 × fS mode.
5 ns BCLK pulse width low.
5 ns BCLK pulse width high.
5 ns LRCLK setup. Time to BCLK rising.
5 ns LRCLK hold. Time from BCLK rising.
5 ns DAC_SDATA setup. Time to BCLK rising.
5 ns DAC_SDATA hold. Time from BCLK rising.
50 ns ADC_SDATA delay. Time from BCLK falling in master mode.
10 MHz CCLK frequency.
10 ns CCLK pulse width low.
10 ns CCLK pulse width high.
5 ns CLATCH setup. Time to CCLK rising.
10 ns CLATCH hold. Time from CCLK rising.
10 ns CLATCH pulse width high.
5 ns CDATA setup. Time to CCLK rising.
5 ns CDATA hold. Time from CCLK rising.
50 ns COUT three-stated. Time from CLATCH rising.
400 kHz SCL frequency.
0.6 μs SCL high.
1.3 μs SCL low.
0.6 μs Setup time; relevant for repeated start condition.
0.6 μs Hold time. After this period, the first clock is generated.
100 ns Data setup time.
300 ns
SCL rise time.
300 ns
SCL fall time.
300 ns
SDA rise time.
300 ns
SDA fall time.
0.6 μs Bus-free time. Time between stop and start.
RLOAD = 1 MΩ, CLOAD = 14 pF.
10 ns Digital microphone clock fall time.
10 ns Digital microphone clock rise time.
22 30 ns Digital microphone delay time for valid data.
0 12 ns Digital microphone delay time for data three-stated.
Rev. C | Page 11 of 80

12 Page





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