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ADP2166 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP2166
Beschreibung Step-Down DC-to-DC Regulators
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
ADP2166 Datasheet, Funktion
Data Sheet
5.5 V, 5 A/6 A, High Efficiency, Step-Down
DC-to-DC Regulators with Output Tracking
ADP2165/ADP2166
FEATURES
Continuous output current
ADP2165: 5 A
ADP2166: 6 A
Integrated MOSFET
High-side on resistance: 19 mΩ
Low-side on resistance: 15 mΩ
Reference voltage: 0.6 V ± 1% over temperature range
Input voltage range: 2.7 V to 5.5 V
Current mode architecture
Switching frequency
Fixed frequency: 620 kHz or 1.2 MHz
Adjustable frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
Selectable synchronize phase shift: in phase or out of phase
External compensation
Programmable soft start
Startup into a precharged output
Voltage tracking input
Power-good output and precision enable input
Accurate current limit
Available in 24-lead, 4 mm × 4 mm LFCSP_WQ package
Supported by ADIsimPower™ design tool
APPLICATIONS
Point of load regulation
Communications and networking
High end consumer
Industrial, instrumentation, and healthcare
GENERAL DESCRIPTION
The ADP2165/ADP2166 are high efficiency, current mode
control, step-down dc-to-dc regulators with an integrated 19 mΩ
high-side FET and a 15 mΩ synchronous rectified FET. The
ADP2165/ADP2166 combine a small size, 4 mm × 4 mm LFCSP
package with an accurate current limit, resulting in a smaller
inductor size and a high power density, point of load solution.
Key features include precision enable, power-good monitor,
and output voltage tracking to facilitate robust sequencing.
The switching frequency can be programmed from 250 kHz
to 1.4 MHz, or it can be fixed at 620 kHz or 1.2 MHz. The
synchronization function allows the switching frequency to
synchronize to an external clock, minimizing the
electromagnetic interference (EMI) of the system.
TYPICAL APPLICATION CIRCUIT
VPVIN
CIN
RRT
CVREG
ADP2165/
PVIN ADP2166 BST
AVIN
EN
SW
PGOOD
SYNC
RT
TRK
FB
COMP
VREG
SS
GND PGND
CBST L1
RTOP
VOUT
COUT
CCP
CSS
RC RBOT
CC
Figure 1.
The ADP2165/ADP2166 are designed to be extremely flexible
with the addition of a minimal amount of external components
to program soft start and control loop compensation.
The ADP2165/ADP2166 are supplied from an input voltage of
2.7 V to 5.5 V. Output voltage options include 3.3 V, 2.5 V, 1.8 V,
1.5 V, 1.2 V, or 1.0 V fixed outputs and adjustableoptions capable
of supporting an output voltage range from 0.6 V to 90% of the
input voltage. Protection features include undervoltage lockout
(UVLO), overvoltage protection (OVP), overcurrent protection
(OCP), and thermal shutdown (TSD) for robust performance.
The ADP2165/ADP2166 operate over the −40°C to +125°C
junction temperature range and are available in a 24-lead
LFCSP_WQ package.
100
VPVIN = 3.3V
95
90
VPVIN = 5V
85
80
75
70
65
60
55 VOUT = 1.8V
fSW = 600kHz
50
0123456
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current
Rev. A
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ADP2166 Datasheet, Funktion
ADP2165/ADP2166
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN, AVIN, EN, PGOOD, FB
SW
BST
SS, COMP, TRK, VREG, SYNC, RT
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−1 V to +6 V
SW + 6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
Table 3. Thermal Resistance
Package Type
24-Lead LFCSP
θJA
38.3
Unit
°C/W
ESD CAUTION
Rev. A | Page 6 of 23

6 Page









ADP2166 pdf, datenblatt
ADP2165/ADP2166
THEORY OF OPERATION
The ADP2165/ADP2166 are step-down, dc-to-dc regulators.
They use a current mode architecturewith an integrated high-side
and low-side switch. They target high performance applications
that require high efficiency and design simplicity.
The ADP2165/ADP2166 can operatewith an input voltage from
2.7 V to 5.5 V and regulate the output voltage down to 0.6 V.
Additional features for flexible design include programmable
switching frequency, programmable soft start, external
compensation, and enable and power-good pins. The
ADP2165/ADP2166 are also available with preset output
voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.
CONTROL SCHEME
The ADP2165/ADP2166 use a fixed frequency, current mode
PWM control architecture for good line and load transient
performance. In fixed frequency PWM mode, adjust the duty
cycle of the integrated MOSFET to regulate the output voltage
that has a low output ripple voltage.
PWM MODE
At the start of each oscillator cycle, the high-side NFET (N-
channel MOSFET) switch turns on and transmits a positive
voltage across the inductor. Current in the inductor increases
until the current sense signal crosses the peak inductor current
level set by the voltage on the COMP pin. The high-side NFET
then turns off, and the low-side NFET synchronous rectifier
then turns on. This puts a negative voltageacross the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle.
ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.2 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.2 V, the regulator turns on, and when it falls below
1.1 V (typical), the regulator turns off. To force the devices to
automatically start when input power is applied, connect the EN
pin to the PVIN pin.
When the ADP2165/ADP2166 are shut down, the soft start
capacitor discharges. When the devices are reenabled, a new
soft start cycle begins.
If the EN pin is not externally connected, an internal pull-down
resistor (1 MΩ) prevents an accidental enable.
Data Sheet
INTERNAL REGULATOR (VREG)
The internal regulator provides a stable supply for the internal
control circuits. It is recommended to place a 1 µF ceramic
capacitor between the VREG and GND pins. The internal
regulator also includes a current-limit circuit to protect the
circuit if the maximum external load is added.
The AVIN pin provides the power supply for the internal regulator.
When device is enabled, the internal regulator is active.
BOOTSTRAP CIRCUITRY
The ADP2165/ADP2166 integrate the boot regulator to provide
the gate drive voltage for the high-sideNFET. A capacitor between
the BST and SW pins is charged from the PVIN pin while the
low-side NFET is on.
Placing an X7R or X5R 0.1 µF ceramic capacitor between the
BST and SW pins is recommended.
OSCILLATOR AND SYNCHRONIZATION
The switching frequency of the ADP2165/ADP2166 can be set
by connecting a resistor between the RT pin and the GND pin.
Use the following equation to set the switching frequency:
RRT (kΩ) = 60,000/[fSW (kHz) + 10] − 5
A 191 kΩ resistor sets the frequency to 300 kHz, and a 93.1 kΩ
resistor sets frequency to 600 kHz. Figure 29 shows the typical
relationship between RRT and fSW.
1600
1400
1200
1000
800
600
400
200
20
40 60 80 100 120 140 160
RRT (kΩ)
Figure 29. Frequency (fSW) vs. RT Resistor
180
To synchronize the ADP2165/ADP2166, drive an external clock
at the SYNC pin. The frequency of the external clock can be in
the 250 kHz to 1.4 MHz range.
During the synchronization, the RT pin can be used to program
the phase shift. When the RT pin is connected to the VREG pin,
the rising edge of the SW pin is 180°out of phase with the external
clock. If the RT pin is floating, the rising edge of the SW pin is in
phase with the external clock.
Rev. A | Page 12 of 23

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