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ADP1873 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1873
Beschreibung PWM Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP1873 Datasheet, Funktion
Data Sheet
Synchronous Current-Mode with
Constant On-Time, PWM Buck Controller
ADP1872/ADP1873
FEATURES
Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 KHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1873 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 µA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.75V TO 20V
CC
RC CC2
VOUT
RTOP
RBOT
CVDD2
VDD = 2.75V
TO 5.5V
CVDD
VIN
ADP1872/
ADP1873
COMP/EN BST
FB DRVH
GND
SW
VDD
DRVL
PGND
CIN
CBST
Q1 L
VOUT
COUT +
Q2
RRES
LOAD
5A
Figure 1.
100
VDD = 5.5V, VIN = 5.5V (PSM)
95
VDD = 5.5V, VIN = 5.5V
90
85
80 VDD = 5.5V, VIN = 13.0V (PSM)
75
VDD = 5.5V, VIN = 16.5V (PSM)
70
65
60
55
50
45
100
TA = 25°C
VOUT = 1.8V
fSW = 300kHz
WURTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k 10k 100k
LOAD CURRENT (mA)
Figure 2. ADP1872 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
GENERAL DESCRIPTION
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current-
mode control architecture. This allows the ADP1872/ADP1873
to drive all N-channel power stages to regulate output voltages
as low as 0.6 V.
The ADP1873 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1873)
section for more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but can also accept a
power input as high as 20 V.
In addition, an internally fixed, soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre-
charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1872/ADP1873 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.






ADP1873 Datasheet, Funktion
ADP1872/ADP1873
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VIN 1
COMP/EN 2
FB 3
GND 4
VDD 5
10 BST
ADP1872
TOP VIEW
(Not to Scale)
9 SW
8 DRVH
7 PGND
6 DRVL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN
High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
3 FB
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
4 GND
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations Section).
5 VDD
Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor
of 1 µF directly from this pin to PGND and a 0.1 µF across VDD and GND are recommended.
6 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 68).
7
PGND
Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
8
DRVH
Drive Output for the External Upper Side, N-Channel MOSFET.
9 SW
Switch Node Connection.
10 BST
Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VDD and BST for increased gate drive capability.
Rev. B | Page 6 of 40

6 Page









ADP1873 pdf, datenblatt
ADP1872/ADP1873
2.658
2.657
2.656
2.655
2.654
2.653
2.652
2.651
2.650
2.649
–40
–20 0
20 40 60 80
TEMPERATURE (°C)
Figure 34. UVLO vs. Temperature
100 120
100
VDD = 2.7V
+125°C
95
90
VDD = 3.6V
VDD = 5.5V
+25°C
–40°C
85
80
75
70
65
60
55
50
45
40
300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
Figure 35. Maximum Duty Cycle vs. Frequency
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
3.6
VDD = 3.6V
VDD = 5.5V
4.8 6.0 7.2 8.4
+125°C
+25°C
–40°C
9.6 10.8 12.0 13.2 14.4 15.6
VIN (V)
Figure 36. Maximum Duty Cycle vs. High Voltage Input (VIN)
Data Sheet
680
VDD = 2.7V
630 VDD = 3.6V
VDD = 5.5V
580
530
480
430
380
330
280
230
180
–40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
Figure 37. Minimum Off-Time vs. Temperature
120
680
+125°C
630
+25°C
–40°C
580
530
480
430
380
330
280
230
180
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V)
Figure 38. Minimum Off-Time vs. VDD (Low Input Voltage)
800
VDD = 2.7V
+125°C
720
VDD = 3.6V
VDD = 5.5V
+25°C
–40°C
640
560
480
400
320
240
160
80
300
400 500 600 700 800 900
FREQUENCY (kHz)
Figure 39. Internal Rectifier Drop vs. Frequency
1000
Rev. B | Page 12 of 40

12 Page





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