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ADP1853 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1853
Beschreibung Step-Down DC-to-DC Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
ADP1853 Datasheet, Funktion
Data Sheet
Synchronous, Step-Down DC-to-DC Controller with
Voltage Tracking and Synchronization
ADP1853
FEATURES
Input voltage range: 2.75 V to 20 V
Output voltage range: 0.6 V to 90% VIN
Maximum output current of more than 25 A
Current mode architecture with current sense input
Configurable to voltage mode
±1% output voltage accuracy over temperature
Voltage tracking input
Programmable frequency: 200 kHz to 1.5 MHz
Synchronization input
Internal clock output
Power saving mode at light load
Precision enable input
Power good with internal pull-up resistor
Adjustable soft start
Programmable current sense gain
Integrated bootstrap diode
Starts into a precharged load
Externally adjustable slope compensation
Suitable for any output capacitor
Overvoltage and overcurrent-limit protection
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 20-lead, 4 mm × 4 mm LFCSP
Supported by ADIsimPower™ design tool
APPLICATIONS
Intermediate bus and POL systems requiring sequencing and
tracking, including
Telecom base station and networking
Industrial and Instrumentation
Medical and healthcare
GENERAL DESCRIPTION
The ADP1853 is a wide range input, dc-to-dc, synchronous
buck controller capable of running from commonly used 3.3 V
to 12 V (up to 20 V) voltage inputs. The device nominally
operates in current mode with valley current sensing providing
the fastest step response for digital loads. It can also be
configured as a voltage mode controller with low noise and
crosstalk for sensitive loads.
The ADP1853 can be used as a master synchronization clock
for the power system and for convenient synchronization
between controllers. The CLKOUT signal can synchronize
other devices in the ADP185x family such that slave devices
are phase-shifted from the master to reduce the input ripple
current, improve EMI, and reduce the size of the input bulk
capacitance. The ADP1853 can also be configured as a slave
device for current sharing. Additionally, the ADP1853 includes
accurate tracking, precision enable, and power good functions
for sequencing. The ADP1853 provides a high speed, high peak
current gate driving capability to enable energy efficient power
conversion. The device can be configured to operate in power
saving mode by skipping pulses, reducing switching losses and
improving efficiency at light load and standby conditions.
The accurate current limit allows design within a narrower
range of tolerances and can reduce overall converter size and
cost. The ADP1853 can regulate down to 0.6 V output using a
high accuracy reference with ±1% tolerance over the
temperature range from −40°C to 125°C.
With a wide range input voltage, the ADP1853 is designed to
provide the designer with maximum flexibility for use in a
variety of system configurations; loop compensation, soft start,
frequency setting, power saving mode, current limit, and
current sense gain can all be programmed using external
components. In addition, the external RAMP resistor allows
choosing optimal slope and VIN feedforward in both current
and voltage mode for excellent line rejection. The linear
regulator and the boot strap diode for the high-side driver are
internal.
Protection features include undervoltage lock out, overvoltage,
overcurrent/short circuit, and overtemperature.
VMA
HI
LO
RRAMP
RAMP
VIN
EN
TRK
VCCO
DH
BST
SW
CS
ILIM
ADP1853
DL
SYNC
FREQ
PGND
FB
SS COMP
VIN
M1
L
M2
RCSG
VOUT
AGND
PGOOD
CLKOUT
Figure 1. Typical Operation Circuit
Rev. A
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Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP1853 Datasheet, Funktion
Data Sheet
Parameter
PGOOD
PGOOD Pull-Up Resistor
PGOOD Delay
Overvoltage or Undervoltage
Minimum Duration
ILIM Threshold Voltage1
ILIM Output Current
Current Sense Blanking Period
INTEGRATED RECTIFIER
(BOOST DIODE) RESISTANCE
ZERO CURRENT CROSS OFFSET
(SW TO PGND)1
1 Guaranteed by design.
2 Connect VIN to VCCO when VIN < 5.5 V.
Symbol
RPGOOD
Test Conditions/Comments
Min
Internal pull-up resistor to VCCO
This is the minimum duration required to trip
the PGOOD signal
Relative to PGND
ILIM = PGND
After DL goes high, current limit is not sensed
during this period
At 20 mA forward current
−5
45
In pulse skip mode only; fOSC = 300 kHz
0
ADP1853
Typ Max Unit
12.5
12
10
0 +5
50 55
100
16
24
kΩ
µs
µs
mV
µA
ns
mV
Rev. A | Page 5 of 28

6 Page









ADP1853 pdf, datenblatt
Data Sheet
SYNC
1
DH
3
CLKOUT
2
CH1 5V BW CH2 5V BW M 1.0µs 1.25GS/s A CH1
CH3 10V BW
400ps/pt
3.6V
Figure 10. Synchronization and CLKOUT, fSYNC = 300 kHz
35
VIN = 12V
34 OUTPUT IS LOADED
HS FET = BSC080N03LS
33 LS FET = BSC030N03LS
32
31
30
29
28
27
26 DEAD TIME BETWEEN SW FALLING EDGE
25 AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 11. Dead Time vs. Temperature
350
300
DH MINIMUM OFF TIME
250
200
150
100
DH MINIMUM ON TIME
50
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
VIN (V)
Figure 12. Typical DH Minimum On Time and Off Time
EN
1
SW
3
ADP1853
VOUT
2
CH1 2V BW CH2 1V BW M 2ms 250kS/s
CH3 10V BW
4µs/pt
A CH1
560mV
Figure 13. Soft Start with Precharged Output, 3.3 VOUT Forced PWM
45
TA = 25°C
43 OUTPUT IS LOADED
HS FET = BSC080N03LS
41 LS FET = BSC030N03LS
39
37
35
33
31
29
27 DEAD TIME BETWEEN SW FALLING EDGE
25 AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
0 5 10 15 20
VIN (V)
Figure 14. Dead Time vs. VIN
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
VIN = 2.75V, SOURCING
VIN = 12V, SOURCING
VIN = 2.75V, SINKING
VIN = 12V, SINKING
–15 10 35 60 85 110
TEMPERATURE (°C)
135
Figure 15. Driver Resistance vs. Temperature
Rev. A | Page 11 of 28

12 Page





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