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ADP1741 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1741
Beschreibung Low Dropout Linear Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP1741 Datasheet, Funktion
Data Sheet
FEATURES
Maximum output current: 2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: 2 µA
Low dropout voltage: 160 mV at 2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start:
0.75 V to 2.5 V (ADP1740)
Adjustable output voltage options with soft start:
0.75 V to 3.3 V (ADP1741)
High PSRR
65 dB at 1 kHz
65 dB at 10 kHz
54 dB at 100 kHz
23 μV rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
APPLICATIONS
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
GENERAL DESCRIPTION
The ADP1740/ADP1741 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to 2 A
of output current. These low VIN/VOUT LDOs are ideal for regu-
lation of nanometer FPGA geometries operating from 2.5 V down
to 1.8 V I/O rails, and for powering core voltages down to 0.75 V.
Using an advanced, proprietary architecture, the ADP1740/
ADP1741 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.
The ADP1740 is available in seven fixed output voltage options.
The ADP1741 is an adjustable version that allows output
2 A, Low VIN, Low Dropout
Linear Regulator
ADP1740/ADP1741
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
VOUT = 1.5V
4.7µF
100kΩ
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1740 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
SENSE 9
PG GND SS NC
5678
10nF
4.7µF
VIN = 1.8V
Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V
VOUT = 0.5V(1 + R1/R2)
4.7µF
100kΩ
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1741 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
PG GND SS
567
ADJ 9
NC
8
4.7µF
R1
R2
10nF
Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.3 V
voltages ranging from 0.75 V to 3.3 V via an external divider.
The ADP1740/ADP1741 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1740/ADP1741 are available in a 16-lead, 4 mm ×
4 mm LFCSP, making them not only very compact solutions,
but also providing excellent thermal performance for applica-
tions that require up to 2 A of output current in a small, low
profile footprint.
Rev. H
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ADP1741 Datasheet, Funktion
ADP1740/ADP1741
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
VIN 1
VIN 2
VIN 3
EN 4
ADP1740
TOP VIEW
12 VOUT
11 VOUT
10 VOUT
9 SENSE
VIN 1
VIN 2
VIN 3
EN 4
ADP1741
TOP VIEW
12 VOUT
11 VOUT
10 VOUT
9 ADJ
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1740 Pin Configuration
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 4. ADP1741 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
ADP1740 ADP1741 Mnemonic
1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN
4 4 EN
5 5 PG
6 6 GND
7 7 SS
8 8 NC
9 SENSE
10, 11, 12,
13, 14
EP
9
10, 11, 12,
13, 14
EP
ADJ
VOUT
Exposed
pad
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all
five VIN pins must be connected to the source supply.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If
the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below
90% of the nominal output voltage, the PG pin immediately transitions low.
Ground.
Soft Start Pin. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense Input. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR
drop between the regulator output and the load.
Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that
all five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad
be connected to the ground plane on the board.
Rev. H | Page 6 of 20

6 Page









ADP1741 pdf, datenblatt
ADP1740/ADP1741
T
1
EN
VOUT
2
500mV/DIV
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 2.0V BW
CH2 500mV BW M40µs A CH1
T 9.8%
920mV
Figure 27. VOUT Ramp-Up with Internal Soft Start
ADJUSTABLE OUTPUT VOLTAGE (ADP1741)
The output voltage of the ADP1741 can be set over a 0.75 V to
3.3 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu-
lated using the following equation:
VOUT = 0.5 V × (1 + R1/R2)
(2)
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA, so to achieve less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.
ENABLE FEATURE
The ADP1740/ADP1741 use the EN pin to enable and disable
the VOUT pins under normal operating conditions. As shown
in Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.
T
EN
VOUT
Data Sheet
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.1
1.0
0.9
EN ACTIVE
0.8
EN INACTIVE
0.7
0.6
0.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
INPUT VOLTAGE (V)
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
The ADP1740/ADP1741 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, or thermal shutdown, or
if it falls below 90% of the nominal output voltage, the power-
good pin (PG) immediately transitions low. During soft start,
the rising threshold of the power-good signal is 93.5% of the
nominal output voltage.
The open-drain output is held low when the ADP1740/ADP1741
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no-good if VOUT falls below 90%.
A normal power-down triggers power no-good when VOUT
drops below 90%.
21
500mV/DIV
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 500mV BW CH2 500mV BW M2.0ms A CH1
T 29.6%
Figure 28. Typical EN Pin Operation
1.05V
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
Rev. H | Page 12 of 20

12 Page





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