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ADP7112 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP7112
Beschreibung CMOS LDO Linear Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 22 Seiten
ADP7112 Datasheet, Funktion
Data Sheet
FEATURES
Low noise: 11 µV rms independent of fixed output voltage
PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,
VOUT = 5 V, VIN = 7 V
Input voltage range: 2.7 V to 20 V
Maximum output current: 200 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature
±1.8%, TJ = −40°C to +125°C
Low dropout voltage: 200 mV (typical) at a 200 mA load,
VOUT = 5 V
User-programmable soft start
Low quiescent current, IGND = 50 μA (typical) with no load
Low shutdown current
1.8 μA at VIN = 5 V
3.0 μA at VIN = 20 V
Stable with a small 2.2 µF ceramic output capacitor
Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V
15 standard voltages between 1.2 V and 5.0 V are available
Adjustable output from 1.2 V to VIN – VDO, output can be
adjusted above initial set point
Precision enable
1 mm × 1.2 mm, 6-ball WLCSP
APPLICATIONS
Regulation to noise sensitive applications
ADC and DAC circuits, precision amplifiers, power for
VCO VTUNE control
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7112 is a CMOS, low dropout (LDO) linear regulator
that operates from 2.7 V to 20 V and provides up to 200 mA of
output current. This high input voltage LDO is ideal for the
regulation of high performance analog and mixed-signal circuits
operating from 20 V down to 1.2 V rails. Using an advanced
proprietary architecture, the device provides high power supply
rejection, low noise, and achieves excellent line and load transient
response with a small 2.2 µF ceramic output capacitor. The
ADP7112 regulator output noise is 11 μV rms, independent of
the output voltage for the fixed options of 5 V or less.
20 V, 200 mA, Low Noise,
CMOS LDO Linear Regulator
ADP7112
TYPICAL APPLICATION CIRCUITS
VIN = 6V
CIN
2.2µF
ON
OFF
ADP7112
VIN VOUT
SENSE/ADJ
EN SS
GND
VOUT = 5V
COUT
2.2µF
CSS
1nF
Figure 1. ADP7112 with Fixed Output Voltage, 5 V
VIN = 7V
CIN
2.2µF
ON
OFF
ADP7112
VIN VOUT
SENSE/ADJ
EN SS
GND
VOUT = 6V
2kΩ
COUT
2.2µF
10kΩ
CSS
1nF
Figure 2. ADP7112 with 5 V Output Adjusted to 6 V
The ADP7112 is available in 15 fixed output voltage options.
The following voltages are available from stock: 1.2 V (adjustable),
1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages available by
special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V,
3.8 V, 4.2 V, and 4.6 V.
Each fixed output voltage can be adjusted above the initial set
point with an external feedback divider. This allows the ADP7112
to provide an output voltage from 1.2 V to VIN − VDO with high
PSRR and low noise.
A user-programmable soft start with an external capacitor is
available in the ADP7112. The ADP7112 is available in a 6-ball
1 mm × 1.2 mm WLCSP, making it a very compact solution.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP7112 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
SENSE/ADJ to GND
SS to GND
Storage Temperature Range
Operating Junction Temperature
(TJ) Range
Operating Ambient Temperature
(TA) Range
Soldering Conditions
Rating
−0.3 V to +24 V
−0.3 V to VIN
−0.3 V to +24 V
−0.3 V to +6 V
−0.3 V to VIN or +6 V
(whichever is less)
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7112 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature can
have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation (PD) of the device, and the
junction-to-ambient thermal resistance of the package (θJA).
Maximum TJ is calculated from the TA and PD using the formula
TJ = TA + (PD × θJA)
(1)
ADP7112
θJA of the package is based on modeling and calculation using a
4-layer board. The θJA is highly dependent on the application and
board layout. In applications where high maximum power
dissipation exists, close attention to thermal board design is
required. The value of θJA can vary, depending on PCB material,
layout, and environmental conditions. The specified values of
θJA are based on a 4-layer, 4 in. × 3 in. circuit board. See JESD51-7
and JESD51-9 for detailed information on the board construction.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance (θJB). Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world app-
lications. Maximum TJ is calculated from the board temperature
(TB) and PD using the formula
TJ = TB + (PD × ΨJB)
(2)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
θJA θJC ΨJB Unit
6-Ball WLCSP
260 4
58 °C/W
ESD CAUTION
Rev. C | Page 5 of 21

6 Page









ADP7112 pdf, datenblatt
Data Sheet
0
–20
–40
–60
–80
–100
–120
3.0V
2.0V
1.6V
1.4V
1.2V
1.0V
800mV
700mV
600mV
500mV
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V,
for Various Headroom Voltages
0
10Hz
–10
100Hz
1kHz
–20
10kHz
100kHz
1MHz
–30 10MHz
–40
–50
–60
–70
–80
–90
–100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
HEADROOM VOLTAGE (V)
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 5 V, for Different Frequencies
20
10Hz TO 100kHz
100Hz TO 100kHz
16
12
8
4
0
1 10 100
LOAD CURRENT (mA)
Figure 30. RMS Output Noise vs. Load Current
1000
ADP7112
10k
1k
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 31. Output Noise Spectral Density vs. Frequency, ILOAD = 10 mA
100k
10k
100µA
1mA
10mA
100mA
200mA
1k
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 32. Output Noise Spectral Density vs. Frequency, for Different Loads
100k
10k
1.8V
3.3V
5.0V
1k
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 33. Output Noise Spectral Density vs. Frequency, for
Different Output Voltages
Rev. C | Page 11 of 21

12 Page





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