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PDF ADP7159 Data sheet ( Hoja de datos )
| Número de pieza | ADP7159 | |
| Descripción | RF Linear Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
ADP7159
FEATURES
Input voltage range: 2.3 V to 5.5 V
Adjustable output voltage range (VOUT): 1.2 V to 3.3 V
Maximum load current: 2 A
Low noise
0.9 μV rms total integrated noise from 100 Hz to 100 kHz
1.6 μV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
68 dB from 1 kHz to 100 kHz
45 dB at 1 MHz
Dropout voltage: 200 mV typical at IOUT = 2 A, VOUT = 3.3 V
Initial accuracy: ±0.6% at ILOAD = 10 mA
Accuracy over line, load, and temperature: ±1.5%
Quiescent current (IGND)
4.0 mA typical at 0 μA
9.0 mA typical at 2 A
Low shutdown current: 0.2 μA typical
Stable with a 10 μF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADP7159 is an adjustable linear regulator that operates from
2.3 V to 5.5 V and provides up to 2 A of output current. Output
voltages from 1.2 V to 3.3 V are possible depending on the model.
Using an advanced proprietary architecture, the device provides
high power supply rejection and ultralow noise, achieving excellent
line and load transient response with only a 10 μF ceramic
output capacitor.
The ADP7159 is available in four models that optimize power
dissipation and PSRR performance as a function of the input
and output voltage. See Table 9 and Table 10 for selection guides.
The typical output noise of the ADP7159 regulator is 0.9 μV rms
from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density
from 10 kHz to 1 MHz. The ADP7159 is available in 10-lead,
3 mm × 3 mm LFCSP and 8-lead SOIC packages, making it not
only a very compact solution, but also providing excellent thermal
performance for applications requiring up to 2 A of output
current in a small, low profile footprint.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
TYPICAL APPLICATION CIRCUIT
VIN = 3.8V
CIN
10µF
ON
OFF
CBYP
1µF
CREG
1µF
ADP7159
VIN VOUT
VOUT_SENSE
EN REF
BYP
REF_SENSE
VREG
GND (EPAD)
VOUT = 3.3V
COUT
10µF
CREF
1µF
R1
VOUT = 1.2V × (R1 + R2)/R2
R2
1kΩ < R2 < 200kΩ
Figure 1. Regulated 3.3 V Output from 3.8 V Input
Table 1. Related Devices
Model
Input Output
Voltage Current
ADP7158 2.3 V to 2 A
5.5 V
ADP7156, 2.3 V to 1.2 A
ADP7157 5.5 V
ADM7150, 4.5 V to 800 mA
ADM7151 16 V
ADM7154, 2.3 V to 600 mA
ADM7155 5.5 V
ADM7160 2.2 V to 200 mA
5.5 V
Fixed/
Adjustable
Fixed
Fixed/
Adjustable
Fixed/
Adjustable
Fixed/
Adjustable
Fixed
Package
10-Lead LFCSP/
8-Lead SOIC
10-Lead LFCSP/
8-Lead SOIC
8-Lead LFCSP/
8-Lead SOIC
8-Lead LFCSP/
8-Lead SOIC
6-Lead LFCSP/
5-Lead TSOT
1k
CCCCBBBBYYYYPPPP
=
=
=
=
1µF
10µF
100µF
1000µF
100
10
1
0.1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP7159
Data Sheet
Parameter
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
VREG THRESHOLDS8
Rising
Falling
Hysteresis
EN INPUT PRECISION
EN Input
Logic High
Logic Low
Logic Hysteresis
LEAKAGE CURRENT
REF_SENSE
EN
Symbol
Test Conditions/Comments
UVLORISE
UVLOFALL
UVLOHYS
VREGUVLORISE
VREGUVLOFALL
VREGUVLOHYS
2.3 V ≤ VIN ≤ 5.5 V
VEN_HIGH
VEN_LOW
VEN_HYS
IREF_SENSE_LKG
IEN_LKG
EN = VIN or ground
Min Typ Max Unit
2.22 2.29 V
1.95 2.02
V
200 mV
1.94 V
1.60 V
185 mV
1.13 1.22 1.31 V
1.05 1.13 1.22 V
90 mV
10
0.01 1
nA
µA
1 VOUT_MAX is the maximum output voltage of each version of the ADP7159.
2 Guaranteed by characterization, but not production tested.
3 This output voltage specification is for ADP7159-04 version. Table 10 provides a guide for selecting one of the four versions of the ADP7159 based on voltage range.
4 This specification is based on an endpoint calculation using 10 mA and 2 A loads.
5 Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage
is the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
6 Dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages
above 2.3 V.
7 Start-up time is the time from the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
8 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
MINIMUM CAPACITANCE
Input1
TA = −40°C to +125°C
CIN
7 10.0
µF
Regulator1
Output1
Bypass
Reference
CREG
COUT
CBYP
CREF
0.7 1.0
7 10.0
0.1 1.0
0.7 1.0
µF
µF
µF
µF
CAPACITOR EFFECTIVE SERIES
RESISTANCE (ESR)
RESR TA = −40°C to +125°C
COUT, CIN
CREG, CREF
CBYP
0.1 Ω
0.2 Ω
2.0 Ω
1 The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 23
5 Page 
ADP7159
0
10Hz
–10
100Hz
1kHz
10kHz
–20 100kHz
1MHz
–30 10MHz
–40
–50
–60
–70
–80
–90
–100
0.50 0.60 0.70 0.80 0.90
HEADROOM (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 3.3 V, 2 A Load
0
ILOAD = 10mA
–10
ILOAD = 100mA
ILOAD = 600mA
–20
ILOAD = 1200mA
ILOAD = 2000mA
–30
–40
–50
–60
–70
–80
–90
–100
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 1.2 V, VIN = 2.4 V
0
1.4V
–10
1.3V
1.2V
1.1V
–20 1.0V
–30
–40
–50
–60
–70
–80
–90
–100
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 1.2 V, 2 A Load
Data Sheet
0
10Hz
–10
100Hz
1kHz
10kHz
–20 100kHz
1MHz
–30 10MHz
–40
–50
–60
–70
–80
–90
–100
1.0 1.1 1.2 1.3 1.4
HEADROOM (V)
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 1.2 V, 2 A Load
0
1µF
–10
10µF
100µF
1000µF
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 2 A Load
2.0
1.8
1.6 10Hz TO 100kHz
1.4
1.2
1.0 100Hz TO 100kHz
0.8
0.6
0.4
0.2
0
10m
100m
1
10
ILOAD (A)
Figure 28. RMS Output Noise vs. Load Current (ILOAD)
Rev. B | Page 10 of 23
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP7159.PDF ] | |
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