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AD5246 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5246
Beschreibung 128-Position I2C-Compatible Digital Resistor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 21 Seiten
AD5246 Datasheet, Funktion
Data Sheet
FEATURES
128 positions
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact, SC70-6 (2 mm × 2.1 mm) package
I2C-compatible interface
Full read/write of wiper register
Power-on preset to midscale
Single-supply 2.7 V to 5.5 V
Rheostat mode temperature coefficient: 45 ppm/°C
Low power, IDD = 0.9 µA at 3.3 V typical
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier-biasing
LCD brightness and contrast adjustment
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5247 provides a compact, 2 mm × 2.1 mm, packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a mechanical
potentiometer or a variable resistor. Available in four different
end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ),
these low temperature coefficient devices are ideal for high
accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C-compatible
digital interface, which can also be used to read back the present
wiper register control word. The 10 kΩ and 100 kΩ options each
128-Position I2C-Compatible
Digital Potentiometer
AD5247
FUNCTIONAL BLOCK DIAGRAM
VDD
SDA
SCL
I2C INTERFACE
A
W
WIPER
REGISTER
B
GND
Figure 1.
have three hard-coded slave address options available to allow
users access to three of these devices on one I2C bus (see Table 8
for a full list of slave address locations).
The resistance between the wiper and either end point of
the fixed resistor varies linearly with respect to the digital
code transferred into the RDAC latch. Note the terms digital
potentiometer, VR (variable resistor), and RDAC are used
interchangeably in this document.
Operating from a 2.7 V to 5.5 V power supply and consuming
0.9 µA (3.3 V) allows the AD5247 to be used in portable
battery-operated applications.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2012 Analog Devices, Inc. All rights reserved.






AD5246 Datasheet, Funktion
Data Sheet
AD5247
Parameter
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
Symbol Conditions
BW
THDW
tS
eN_WB
RAB = 10 kΩ/50 kΩ/100 kΩ,
code = 0x40
VA =1 V rms, f = 1 kHz, RAB = 10 kΩ
VA = 5 V ±1 LSB error band
RWB = 5 kΩ, RS = 0
Min Typ1
Max Unit
600/100/40
0.05
2
9
kHz
%
µs
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design, not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter1, 2, 3
SCL Clock Frequency
Bus Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA5
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
Symbol
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Min Typ4 Max Unit
400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 50 µs
0.6 µs
0.9 µs
100 ns
300 ns
300 ns
0.6 µs
1 Specifications apply to all parts.
2 Guaranteed by design, not subject to production test.
3 See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.
4 Typical specifications represent average readings at 25°C and VDD = 5 V.
5 After this period, the first clock pulse is generated.
SCL
t2
SDA
t1
PS
t8
t3
t8
t6
t9
t9
t4
t7
t2
t5
S
Figure 2. I2C Interface, Detailed Timing Diagram
t10
P
Rev. F | Page 5 of 20

6 Page









AD5246 pdf, datenblatt
Data Sheet
0.30
A-VDD = 5.5V
CODE = 0x55
0.25
B-VDD = 5.5V
CODE = 0x7F
0.20 C-VDD = 2.7V
CODE = 0x55
0.15 D-VDD = 2.7V
CODE = 0x7F
TA = 25°C
0.10
0.05
0
1k
A
B
10k 100k
FREQUENCY (Hz)
Figure 22. IDD vs. Frequency
C
D
1M
150
TA = 25°C
RAB = 50k
125
100
VDD = 2.7V
75
50
25 VDD = 5.5V
0
0 16 32 48 64 80 96 112 128
CODE (Decimal)
Figure 23. Wiper Resistance vs. Code vs. VDD
VDD = 5.5V
VA = 5.0V
VB = 0V
TA = 25°C
RAB = 10k
FCLK = 100kHz
VW
CLK
5V
0V
1µs/DIV
Figure 24. Digital Feedthrough
VDD = 5.5V
VA = 5.0V
VB = 0V
CODE 0x40 TO CODE 0x3F
AD5247
TA = 25°C
RAB = 10kΩ
VW
200ns/DIV
Figure 25. Midscale Glitch, Code 0x40 to Code 0x3F
VDD = 5.5V
VA = 5.0V
VB = 0V
CODE 0x00 TO CODE 0x7F
TA = 25°C
RAB = 10k
VW
4µs/DIV
Figure 26. Large Signal Settling Time
Rev. F | Page 11 of 20

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