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PDF AD9789 Data sheet ( Hoja de datos )
| Número de pieza | AD9789 | |
| Descripción | 14-Bit 2400 MSPS RF DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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14-Bit, 2400 MSPS RF DAC
with 4-Channel Signal Processing
AD9789
FEATURES
DOCSIS 3.0 performance: 4 QAM carriers
ACLR over full band (47 MHz to 1 GHz)
−75 dBc @ fOUT = 200 MHz
−72 dBc @ fOUT = 800 MHz (noise)
−67 dBc @ fOUT = 800 MHz (harmonics)
Unequalized MER = 42 dB
On chip and bypassable
4 QAM encoders with SRRC filters, 16× to 512× interpolation,
rate converters, and modulators
Flexible data interface: 4, 8, 16, or 32 bits wide with parity
Power: 1.6 W (IFS = 20 mA, fDAC = 2.4 GHz, LVDS interface)
Direct to RF synthesis support with fS mix mode
Built-in self-test (BIST) support
Input connectivity check
Internal random number generator
APPLICATIONS
Broadband communications systems
CMTS/DVB
Cellular infrastructure
Point-to-point wireless
GENERAL DESCRIPTION
The AD9789 is a flexible QAM encoder/interpolator/upconverter
combined with a high performance, 2400 MSPS, 14-bit RF digital-
to-analog converter (DAC). The flexible digital interface can
accept up to four channels of complex data. The QAM encoder
supports constellation sizes of 16, 32, 64, 128, and 256 with
SRRC filter coefficients for all standards.
The on-chip rate converter supports a wide range of baud rates
with a fixed DAC clock. The digital upconverter can place the
channels from 0 to 0.5 × fDAC. This permits four contiguous
channels to be synthesized and placed anywhere from dc to fDAC/2.
The AD9789 includes a serial peripheral interface (SPI) for
device configuration and status register readback. The flexible
digital interface can be configured for data bus widths of 4, 8,
16, and 32 bits. It can accept real or complex data.
The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for
a total power consumption of 1.6 W. It is supplied in a 164-ball
chip scale package ball grid array for lower thermal impedance
and reduced package parasitics. No special power sequencing
is required. The clock receiver powers up muted to prevent
start-up noise.
PRODUCT HIGHLIGHTS
1. Highly integrated and configurable QAM mappers, inter-
polators, and upconverters for direct synthesis of one to
four DOCSIS- or DVB-C-compatible channels in a block.
2. Low noise and intermodulation distortion (IMD) perfor-
mance enable high quality synthesis of signals up to 1 GHz.
3. Flexible data interface supports LVDS for improved SFDR
or CMOS input data for less demanding applications.
4. Interface is configurable from 4-bit nibbles to 32-bit words
and can run at up to 150 MHz CMOS or 150 MHz LVDS
double data rate (DDR).
5. Manufactured on a CMOS process, the AD9789 uses a
proprietary switching technique that enhances dynamic
performance.
32 INPUT
PINS
AND
2 PARITY
PINS
DCO
CMOS
0 TO 15
LVDS
RISE
150MHz
LVDS/CMOS
CMOS
16 TO 31
LVDS
FALL
FS
FUNCTIONAL BLOCK DIAGRAM
DATA
QAM/
FILTER/
NCO
RETIMER
DATA FORMATTER/
ASSEMBLER
DATA
DATA
QAM/
FILTER/
NCO
QAM/
FILTER/
NCO
DATA
QAM/
FILTER/
NCO
Figure 1.
16×
INTERPOLATOR
AND BPF
+ SCALARS
14-BIT
2.4GSPS
DAC
SPI
IRQ RS
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009-2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9789
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
DAC RESOLUTION
ANALOG OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current (Monotonicity Guaranteed)
Output Compliance Range
Output Resistance
Output Capacitance
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance1
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
DVDD15
SUPPLY CURRENTS AND POWER DISSIPATION
fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled
IAVDD33
IDVDD18
ICVDD18
IDVDD33
CMOS Interface
LVDS Interface
IDVDD15
fDAC = 2.0 GSPS, fOUT = 70 MHz, IFS = 20 mA, CMOS Interface
IAVDD33
IDVDD18
ICVDD18
IDVDD33
IDVDD15 (Four Channels Enabled, All Signal Processing Enabled)
IDVDD15 (One Channel Enabled, 16× Interpolation Only)
Power Dissipation
fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled
CMOS Interface
LVDS Interface
Min
8.66
−1.0
3.14
1.71
3.14
1.71
1.43
Typ
14
6.5
3.5
20.2
70
1
135
25
1.2
5
3.3
1.8
3.3
1.8
1.5
45
72
180
42
16
640
37.4
67.3
155.4
40.3
517
365
1.7
1.63
Max
31.66
+1.0
3.47
1.89
3.47
1.89
1.58
38.5
70.5
180
50.7
556
391
Unit
Bits
% FSR
% FSR
mA
V
Ω
pF
ppm/°C
ppm/°C
V
kΩ
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
W
1 Use an external amplifier to drive any external load.
Rev. A | Page 4 of 76
5 Page 
AD9789
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
A1, A2, A3, A6, A9, A10, A11,
B1, B2, B3, B6, B7, B8, B9,
B10, B11, C2, C3, C6, C7, C8,
C9, C10, C11, D2, D3, D6, D7,
D8, D9, D10, D11, E1, E2, E3,
E4, E13, E14, F1, F2, F3, F4,
F11, F12, F13, F14
AVSS
A4, A5, B4, B5, C4, C5, D4, D5 CVDD18
A7 IOUTN
A8 IOUTP
A12, A13, B12, B13, C12, C13, AVDD33
D12, D13
A14 NC
B14 I120
C1 CLKN
C14 VREF
D1 CLKP
D14 IPTAT
E11, E12
G1, G2, G3, G4, G7, G8, G11,
G12, G13, G14
H1, H2, H3, H4, H7, H8, H11,
H12, H13, H14, J1, J2, J3, J4,
J11, J12, J13, J14
K1, K2, K3, K4, K11, K12, K13,
K14
L1
L2, L3, M2, M3, N3, N4, P3, P4
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
DVDD18
DVDD15
DVSS
DVDD33
CS
NC
P1/PARP
D31/D15P
D27/D13P
D23/D11P
D19/D9P
D15/D7P
D11/D5P
D7/D3P
D3/D1P
FSP
CMOS_BUS
M1 SCLK
M4 P0/PARN
M5 D30/D15N
M6 D26/D13N
M7 D22/D11N
M8 D18/D9N
M9 D14/D7N
M10 D10/D5N
M11 D6/D3N
M12 D2/D1N
M13 FSN
Description
Analog Supply Ground.
1.8 V Clock Supply.
DAC Negative Output Current.
DAC Positive Output Current.
3.3 V Analog Supply.
No Connect. Leave floating.
Tie this pin to analog ground with a 10 kΩ resistor to generate a 120 μA reference current.
Negative DAC Clock Input (DACCLK).
Band Gap Voltage Reference I/O. Decouple to analog ground with a 1 nF capacitor.
Output impedance is approximately 5 kΩ.
Positive DAC Clock Input (DACCLK).
Factory Test Pin. Output current, proportional to absolute temperature, is
approximately 10 μA at 25°C with a slope of approximately 20 nA/°C.
1.8 V Digital Supply.
1.5 V Digital Supply.
Digital Supply Ground.
3.3 V Digital Supply.
Active Low Chip Select for SPI.
Not Used. Leave unconnected.
CMOS/LVDS Parity Bit.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Positive LVDS Frame Sync (FSP) for Data Bus.
Active High Input. Configures data bus for CMOS inputs. Low input configures data bus
to accept LVDS inputs.
Qualifying Clock for SPI.
CMOS/LVDS Parity Bit.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Negative LVDS Frame Sync (FSN) for Data Bus.
Rev. A | Page 10 of 76
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9789.PDF ] | |
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