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PDF AD5339 Data sheet ( Hoja de datos )
| Número de pieza | AD5339 | |
| Descripción | 8-/10-/12-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5339 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2-wire (I2C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at VDD < 3.6 V. Multiple devices
can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN
LDAC
SCL
SDA
A0
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTA
VOUTB
POWER-ON
RESET
AD5337/AD5338/AD5339
GND
Figure 1.
POWER-DOWN
LOGIC
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
1 page  
AD5337/AD5338/AD5339
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2, 3
Output Voltage Settling Time
AD5337
AD5338
AD5339
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A Version and B Version1
Min Typ Max
68
79
8 10
0.7
12
1
1
3
200
−70
Unit Conditions/Comments
VREF = VDD = 5 V
μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
μs 1/4 scale to 3/4 scale change (0x100 to 0x300)
μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
V/μs
nV-s 1 LSB change around major carry
nV-s
nV-s
nV-s
kHz VREF = 2 V ± 0.1 V p-p
dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Temperature range for A version and B version: −40°C to +105°C; typical at 25°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section for explanations of the specific parameters.
Rev. C | Page 5 of 28
5 Page 
300
–40°C
250
200 +25°C +105°C
150
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 16. Supply Current vs. Supply Voltage
5.5
0.5
0.4
0.3
–40°C
0.2
+25°C
0.1
+105°C
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 17. Power-Down Current vs. Supply Voltage
5.5
400
TA = 25°C
350
VDD = 5V
300
DECREASING
250 INCREASING
200 VDD = 3V
150
100
50
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VLOGIC (V)
Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage
Increasing and Decreasing
AD5337/AD5338/AD5339
TA = 25°C
VDD = 5V
VREF = 5V
CH1
VOUTA
CH2
SCL
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 19. Midscale Settling (¼ to ¾ Scale Code Change)
TA = 25°C
VDD = 5V
VREF = 2V
CH1
VDD
CH2 VOUTA
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV
Figure 20. Power-On Reset to 0 V
TA = 25°C
VDD = 5V
VREF = 2V
CH1
CH2
VOUTA
SCL
CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Existing Power-Down to Midscale
Rev. C | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5339.PDF ] | |
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