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AD5337 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5337
Beschreibung 8-/10-/12-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD5337 Datasheet, Funktion
2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2-wire (I2C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at VDD < 3.6 V. Multiple devices
can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN
LDAC
SCL
SDA
A0
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTA
VOUTB
POWER-ON
RESET
AD5337/AD5338/AD5339
GND
Figure 1.
POWER-DOWN
LOGIC
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.






AD5337 Datasheet, Funktion
AD5337/AD5338/AD5339
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCL
t1
t2
t3
t4
t5
t6 1
t7
t8
t9
t10
t11
CB
Limit at TMIN, TMAX
A Version and B Version
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 CB2
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
SCL
t4
START
CONDITION
t10 t11
t4
t6 t2
t5
t7
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
t1
t8
STOP
CONDITION
Rev. C | Page 6 of 28

6 Page









AD5337 pdf, datenblatt
AD5337/AD5338/AD5339
VDD = 3V
VDD = 5V
150 200 250 300
IDD (µA)
Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V
2.50
2.49
2.48
2.47
1µs/DIV
Figure 23. AD5339 Major Code Transition Glitch Energy
10
0
–10
–20
–30
–40
–50
–60
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)
0.02
TA = 25°C
VDD = 5V
0.01
0
–0.01
–0.02
0
1234
VREF (V)
Figure 25. Full-Scale Error vs. VREF
5
6
50ns/DIV
Figure 26. DAC-to-DAC Crosstalk
Rev. C | Page 12 of 28

12 Page





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