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PDF AD5382 Data sheet ( Hoja de datos )
| Número de pieza | AD5382 | |
| Descripción | 14-Bit denseDAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
32-Channel, 3 V/5 V, Single-Supply,
14-Bit denseDAC
AD5382
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I2C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
DVDD (×3)
DGND (×3)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×4)
AGND (×4) DAC_GND (×4)
REFGND
REFOUT/REFIN SIGNAL_GND (×4)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I2C)
DB10
DB0
A4
A0
REG0
REG1
RESET
BUSY
CLR
AD5382
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
VOUT0………VOUT31
MON_IN1
MON_IN2
MON_IN3
MON_IN4
36-TO-1
MUX
14 INPUT 14
REG0
14
14
m REG0
c REG0
14 INPUT 14
REG1
14
14
m REG1
c REG1
14 INPUT 14
REG6
14
14
m REG6
c REG6
14 INPUT 14
REG7
14
14
m REG7
c REG7
×4
1.25V/2.5V
REFERENCE
14
DAC 14
REG0
DAC 0
14
DAC 14
REG1
DAC 1
14
DAC 14
REG6
DAC 6
14
DAC 14
REG7
DAC 7
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT31
MON_OUT
Figure 1.
LDAC
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5382
GENERAL DESCRIPTION
The AD5382 is a complete, single-supply, 32-channel, 14-bit
denseDAC® available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation. The
AD5382 includes an internal software-selectable 1.25 V/2.5 V,
10 ppm/°C reference, an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring, and an output amplifier boost mode
that allows optimization of the amplifier slew rate.
The AD5382 contains a double-buffered parallel interface,
which features a 20 ns WR pulse width, an SPI-, QSPI-,
Data Sheet
MICROWIRE-, DSP-compatible serial interface with
interface speeds in excess of 30 MHz and an I2C®-compatible
interface that supports a 400 kHz data transfer rate.
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated
independently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC
channel. Power consumption is typically 0.25 mA per channel
when operating with boost mode disabled.
Rev. D | Page 4 of 40
5 Page 
AD5382
SCLK
SYNC
DIN
SDO
SCLK
SYNC
t4
t7
t3
t6
t8 t9
t1
24
t2 t5
24
DIN
BUSY
LDAC1
VOUT1
LDAC2
VOUT2
DB23
DB0
t10
t11
t12 t13
t15
t17
t14
t13
t16 t17
CLR
t18
t19
VOUT
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
24
t7A
48
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
NOP CONDITION
DB0
UNDEFINED
SELECTED REGISTER
DATA CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
Data Sheet
Rev. D | Page 10 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5382.PDF ] | |
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