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PDF AD5316R Data sheet ( Hoja de datos )
| Número de pieza | AD5316R | |
| Descripción | Quad 10-Bit nanoDAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Quad, 10-Bit nanoDAC with 2 ppm/°C
Reference, I2C Interface
AD5316R
FEATURES
Low drift 2.5 V on-chip reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
400 kHz I2C-compatible serial interface
4 I2C addresses available
Low glitch: 0.5 nV-sec
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5316R, a member of the nanoDAC® family, is a low power,
quad, 10-bit buffered voltage output DAC. The device includes
a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a
gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V
(gain = 2). The device operates from a single 2.7 V to 5.5 V supply,
is guaranteed monotonic by design, and exhibits less than 0.1%
FSR gain error and 1.5 mV offset error performance. The device
is available in a 3 mm × 3 mm LFCSP package and in a TSSOP
package.
The AD5316R also incorporates a power-on reset circuit and a
RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power
up to zero scale or midscale and remain at that level until a valid
write takes place. The part contains a per-channel power-down
feature that reduces the current consumption of the device in
power-down mode to 4 µA at 3 V.
The AD5316R uses a versatile 2-wire serial interface that operates
at clock rates up to 400 kHz and includes a VLOGIC pin intended
for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
A1
A0
AD5316R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
12-Bit
AD5684R
AD5684
AD5694R
AD5694
10-Bit
AD5317R
AD5317
AD53161
1 The AD5316R and the AD5316 are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5316R
Data Sheet
Parameter
LOGIC OUTPUTS (SDA)4
Output Low Voltage, VOL
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode10
All Power-Down Modes11
Min Typ
4
1.8
2.7
VREF + 1.5
0.59
1.1
1
Max
0.4
5.5
3
5.5
5.5
0.7
1.3
4
6
Unit
V
pF
V
µA
V
V
mA
mA
µA
µA
Test Conditions/Comments1, 2
ISINK = 3 mA
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
−40°C to +105°C
1 Temperature range is −40°C to +105°C.
2 The AD5316R and the AD5316 are not pin-to-pin or software compatible.
3 DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD
with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
4 Guaranteed by design and characterization; not production tested.
5 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
6 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum junction temperature may impair device reliability.
7 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 25).
8 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Solder Heat Reflow section.
9 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. Reference temperature coefficient is calculated as per the box method.
See the Terminology section for more information.
10 Interface inactive. All DACs active. DAC outputs unloaded.
11 All DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
Min Typ Max Unit Test Conditions/Comments3
5 7 µs ¼ to ¾ scale settling to ±1 LSB
0.8 V/µs
0.5
nV-sec
1 LSB change around major carry transition
0.13 nV-sec
0.1 nV-sec
0.2 nV-sec
0.3 nV-sec
−80 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
300
nV/√Hz
DAC code = midscale, 10 kHz, gain = 2
6
µV p-p
0.1 Hz to 10 Hz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C; typical at 25°C.
4 Digitally generated sine wave at 1 kHz.
Rev. B | Page 4 of 24
5 Page 
AD5316R
1.4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
1.2
1.0
0.8
0.6
0.4 ZERO-CODE ERROR
0.2
OFFSET ERROR
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 17. Zero-Code Error and Offset Error vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
–0.02
GAIN ERROR
FULL-SCALE ERROR
–0.04
–0.06
–0.08
–0.10
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7 4.2
4.7
SUPPLY VOLTAGE (V)
5.2
Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage
1.5
1.0
0.5
ZERO-CODE ERROR
0
OFFSET ERROR
–0.5
–1.0
–1.5
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7 4.2
4.7
SUPPLY VOLTAGE (V)
5.2
Figure 19. Zero-Code Error and Offset Error vs. Supply Voltage
Data Sheet
0.10
0.09
0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 20. TUE vs. Temperature
100 120
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 21. TUE vs. Supply Voltage, Gain = 1
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
0 156 312 468
624
CODE
Figure 22. TUE vs. Code
780
936 1023
Rev. B | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD5316R.PDF ] | |
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