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PDF AD5338R Data sheet ( Hoja de datos )

Número de pieza AD5338R
Descripción Dual 10-Bit nanoDAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
Dual, 10-Bit nanoDAC
with 2 ppm/°C Reference, I2C Interface
AD5338R
FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of full-scale range (FSR)
maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process controls (programmable logic controller [PLC] I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5338R, a member of the nanoDAC® family, is a low power,
dual, 10-bit buffered voltage output digital-to-analog converter
(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference
(enabled by default) and a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5338R operates from
a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,
and exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.
The AD5338R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to zero
scale or midscale and remain there until a valid write takes place.
It contains a per channel power-down feature that reduces the
current consumption of the device to 4 µA at 3 V while in power-
down mode.
The AD5338R uses a versatile 2-wire serial interface that operates
at clock rates up to 400 kHz and includes a VLOGIC pin intended
for 1.8 V/3 V/5 V logic.
VLOGIC
SCL
SDA
A1
A0
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5338R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
BUFFER
BUFFER
VOUTA
VOUTB
POWER-ON
RESET
GAIN =
×1/×2
POWER-
DOWN
LOGIC
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
12-Bit
AD5687R
AD5687
AD5697R
10-Bit
AD5313R1
AD53131
AD5338R1
AD53381
1 The AD5338R and the AD5338 are not pin-to-pin or software compatible. The
AD5313R and the AD5313 are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




AD5338R pdf
AD5338R
Data Sheet
Parameter
Min Typ Max
LOGIC OUTPUTS (SDA)2
Output Low Voltage, VOL
0.4
Floating State Output Capacitance
4
POWER REQUIREMENTS
VLOGIC
1.8 5.5
ILOGIC
3
VDD 2.7 5.5
VREF + 1.5
5.5
IDD
Normal Mode9
0.59 0.7
1.1 1.3
All Power-Down Modes10
14
6
Unit Test Conditions/Comments
V ISINK = 3 mA
pF
V
µA
V Gain = 1
V Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
mA Internal reference off
mA Internal reference on, at full scale
µA −40°C to +85°C
µA −40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with
gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
2 Guaranteed by design and characterization; not production tested.
3 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA up to a junction temperature of 100°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during
current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output device.
For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26).
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. Both DACs active. DAC outputs unloaded.
10 Both DACs powered down.
Rev. 0 | Page 4 of 28

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AD5338R arduino
AD5338R
2.5002
2.5000
TA = 25°C
D1
2.4998
2.4996
D3
2.4994
2.4992
D2
2.4990
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Figure 11. Internal Reference Voltage vs. Supply Voltage
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
156 312 468 625 781
CODE
Figure 12. Integral Nonlinearity (INL)
938
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
156 312 468 625 781
CODE
Figure 13. Differential Nonlinearity (DNL)
938
Data Sheet
0.15
0.12
0.09
0.06
0.03
0
–0.03
INL
DNL
–0.06
–0.09
–0.12
–0.15
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–40 10
60
110
TEMPERATURE (°C)
Figure 14. INL Error and DNL Error vs. Temperature
0.15
0.12
0.09
0.06
0.03
0
–0.03
INL
DNL
–0.06
–0.09
–0.12
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.15
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VREF (V)
Figure 15. INL Error and DNL Error vs. VREF
4.5
5.0
0.15
0.12
0.09
0.06
0.03
0
–0.03
INL
DNL
–0.06
–0.09
–0.12
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.15
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 16. INL Error and DNL Error vs. Supply Voltage
Rev. 0 | Page 10 of 28

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