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PDF AD5676 Data sheet ( Hoja de datos )
| Número de pieza | AD5676 | |
| Descripción | 16-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
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Data Sheet
Octal, 16-Bit nanoDAC+ with SPI Interface
AD5676
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
The AD5676 is a low power, octal, 16-bit buffered voltage
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
Table 1. Octal nanoDAC+® Devices
Interface Reference 16-Bit
SPI
Internal
AD5676R
External
AD5676
I2C
Internal
AD5675R
External
AD5675
12-Bit
AD5672R
Not applicable
AD5671R
Not applicable
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: ±3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
VREF
AD5676
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
BUFFER
VOUT0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
BUFFER
VOUT1
SCLK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
BUFFER
VOUT2
SYNC
SDI
INTERFACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC 3
STRING
DAC 4
BUFFER
BUFFER
VOUT3
VOUT4
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
BUFFER
VOUT5
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
BUFFER
VOUT6
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
BUFFER
VOUT7
POWER-ON RESET
GAIN x1/x2
POWER-DOWN
LOGIC
RSTSEL
Figure 1.
GAIN
GND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD5676
Data Sheet
Parameter
LOGIC INPUTS3
Input Current
Input Voltage
Low, VINL
High, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Voltage
Low, VOL
High, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode7
All Power-Down Modes8
A Grade
Min Typ Max
±1
0.7 ×
VLOGIC
3
0.3 ×
VLOGIC
VLOGIC −
0.4
4
0.4
1.8
2.7
VREF +
1.5
1.1
1.1
1
1
1
1
1
1
5.5
3
3
3
3
5.5
5.5
1.26
1.3
1.7
1.7
2.5
2.5
5.5
5.5
Min
0.7 ×
VLOGIC
B Grade
Typ Max
±1
0.3 ×
VLOGIC
3
VLOGIC −
0.4
4
0.4
1.8
2.7
VREF +
1.5
1.1
1.1
1
1
1
1
1
1
5.5
3
3
3
3
5.5
5.5
1.26
1.3
1.7
1.7
2.5
2.5
5.5
5.5
Unit
µA
V
V
pF
V
V
pF
V
µA
µA
µA
µA
V
V
mA
mA
µA
µA
µA
µA
µA
µA
Test Conditions/Comments
Per pin
ISINK = 200 μA
ISOURCE = 200 μA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
−40°C to +85°C
−40°C to +105°C
Three-state, −40°C to +85°C
Power down to 1 kΩ, −40°C to
+85°C
Three-state, −40°C to +105°C
Power down to 1 kΩ, −40°C to
+105°C
Three-state, −40°C to +125°C
Power down to 1 kΩ, −40°C to
+125°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 See the Terminology section.
3 Guaranteed by design and characterization; not production tested.
4 Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink
40 mA up to a junction temperature of 125°C.
5 VDD = 5 V. The AD5676 includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
7 Interface inactive. All DACs active. DAC outputs unloaded.
8 All DACs powered down.
Rev. B | Page 4 of 27
5 Page 
AD5676
Data Sheet
VDD 1
VLOGIC 2
SYNC 3
SCLK 4
SDI 5
AD5676
TOP VIEW
(Not to Scale)
15 VREF
14 RESET
13 SDO
12 LDAC
11 GND
NIC = NOT INTERNALLY CONNECTED
Figure 6. 20-Lead LFCSP Pin Configuration
Table 8. 20-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD
Power Supply Input. The AD5676 operate from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a
0.1 µF capacitor to GND.
2 VLOGIC Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
3 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data
transfers in on the falling edges of the next 24 clocks.
4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
5 SDI
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
6 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
7 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
8 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
9 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
10, 16 NIC
Not Internally Connected
11 GND
Ground Reference Point for All Circuitry on the Device.
12 LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data. That allows all DAC outputs to simultaneously
update. This pin can also be tied permanently low.
13 SDO
Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
14 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
15 VREF
Reference Input Voltage.
17 VOUT3
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
18 VOUT2
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
19 VOUT1
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
20 VOUT0
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
EPAD
Exposed Pad. The exposed pad must be tied to GND.
Rev. B | Page 10 of 27
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5676.PDF ] | |
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