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PDF ADL5336 Data sheet ( Hoja de datos )
| Número de pieza | ADL5336 | |
| Descripción | Cascadable IF VGAs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Pair of VGAs with rms AGC detectors
VGA and AGC modes of operation
Continuous gain control range: 48 dB
Noise figure (NF) = 6.8 dB at maximum gain
IMD3 > 62 dBc for 1.0 V p-p composite output
Differential input and output
Multiplexed inputs for VGA2
Programmable detector AGC setpoints
Programmable VGA maximum gain
Power-down feature
Single 5 V supply operation
APPLICATIONS
Point-to-multipoint radios
Instrumentation
Medical
GENERAL DESCRIPTION
The ADL5336 consists of a pair of variable gain amplifiers
(VGAs) designed for cascaded IF applications. The amplifiers
have linear-in-dB gain control and operate from low frequencies to
1 GHz. Their excellent gain conformance over the control range
and flatness over frequency are due to Analog Devices, Inc.,
patented X-AMP® architecture, an innovative technique for
implementing high performance variable gain control.
Each VGA has 24 dB of gain control range. Their maximum gain
can be independently programmable over a 6 dB range via the
SPI. The VGAs can be cascaded to provide a total range of 48 dB.
When connected to a 50 Ω source through a 1:4 balun, the gain
is 6 dB higher. The second VGA has an SPI programmable input
switch that selects one of two external inputs.
Cascadable IF VGAs with
Programmable RMS Detectors
ADL5336
FUNCTIONAL BLOCK DIAGRAM
COM OPP1 OPM1 IP2A IM2A COM IP2B IM2B
VCM1
VPOS
INP1
VGA1
INM1
VPOS
COM
MODE
ENBL
X2
VGA2
X2
ADL5336
SPI
VCM2
VPOS
OPP2
OPM2
VPOS
COM
SDO
DATA
GAIN1 DTO1 GAIN2 DTO2 COMD VPSD LE CLK
Figure 1.
When driven from a 200 Ω source or from a 50 Ω source through
a 1:4 balun, the noise figure (NF) for the composite amplifier is
6.8 dB at maximum gain. The output of each VGA can drive
100 Ω loads to 5 V p-p maximum.
Each VGA has an independent square law detector for autonomous,
automatic gain control (AGC) operation. Each detector setpoint
can be programmed independently through the SPI from −24 dBV
to −3 dBV in 3 dB steps. When both VGAs are arranged in AGC
mode and are programmed to the same setpoint, the composite NF
increases to 9 dB when backed off by 18 dB from maximum gain.
The ADL5336 operates from a 5 V supply and consumes a typical
supply current of 80 mA. When disabled, it consumes 4 mA. It is
fabricated in an advanced silicon-germanium BiCMOS process and
is available in a 32-lead exposed paddle LFCSP package. Performance
is specified over a −40°C to +85°C temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
TIMING DIAGRAMS
tCLK
tPW
CLK
LE
DATA
tLS
tDS tDH
WRITE BIT
LSB
tLH
LSB + 1
LSB + 2
LSB + 3
MSB – 3
MSB – 2
MSB – 1
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING
EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
ADL5336
CLK
tD
tLS
tCLK
tPW
tLH
LE
tDS tDH
DATA
READ BIT
DC
DC
DC
DC
DC
DC
DC
DC
SDO
LSB
LSB + 1
LSB + 2
LSB + 3
MSB – 3
MSB – 2
MSB – 1
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES
OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Rev. B | Page 5 of 32
5 Page 
Data Sheet
12 5
10 3
81
6 –1
4 –3
2 –5
0 –7
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VPOS (V)
Figure 23. OP1dB vs. Supply Voltage for VGA1
40
4.5Vdc/–40°C
5.0Vdc/–40°C
35 5.5Vdc/–40°C
4.5Vdc/+25°C
5.0Vdc/+25°C
30 5.5Vdc/+25°C
4.5Vdc/+85°C
5.0Vdc/+85°C
25 5.5Vdc/+85°C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGAIN1 (V)
Figure 24. Noise Figure vs. VGAIN1 over Supply and Temperature for VGA1
13
12
11
10
9
8
7
6
5
GAIN CODE 00
4
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
3
0 100 200 300 400 500 600 700 800
FREQUENCY (MHz)
Figure 25. Noise Figure vs. Frequency over Maximum Gains for VGA1
ADL5336
16 6
14 4
12 2
10 0
8 –2
6 –4
4 –6
2 –8
0 –10
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VPOS (V)
Figure 26. OP1dB vs. Supply Voltage for VGA2
40
4.5Vdc/–40°C
5.0Vdc/–40°C
35 5.5Vdc/–40°C
4.5Vdc/+25°C
5.0Vdc/+25°C
30 5.5Vdc/+25°C
4.5Vdc/+85°C
5.0Vdc/+85°C
25 5.5Vdc/+85°C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGAIN2 (V)
Figure 27. Noise Figure vs. VGAIN2 over Supply and Temperature for VGA2
15
14
13
12
11
10
9
8
7
GAIN CODE 00
6
GAIN CODE 01
GAIN CODE 10
GAIN CODE 11
5
0 100 200 300 400 500 600 700 800
FREQUENCY (MHz)
Figure 28. Noise Figure vs. Frequency over Maximum Gains for VGA2
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADL5336.PDF ] | |
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