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ADM1278 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1278
Beschreibung Hot Swap Controller and Digital Power and Energy Monitor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADM1278 Datasheet, Funktion
Data Sheet
Hot Swap Controller and Digital Power and
Energy Monitor with PMBus Interface
ADM1278
FEATURES
±0.3% accurate, 12-bit ADC for IOUT, VIN, VOUT, and temperature
320 ns response time to short circuit
Shutdown on detection of FET health fault
Constant power foldback for tighter FET SOA protection
Remote temperature sensing with programmable warning
and shutdown thresholds
Resistor-programmable 5 mV to 25 mV VSENSE current limit
Programmable start-up current limit
1% accurate UV, OV, and PWRGD thresholds
Split hot swap and power monitor inputs to allow additional
external ADC filtering
Reports power and energy consumption over time
Peak detect registers for current, voltage, and power
PROCHOT power throttling capability
PMBus fast mode compliant interface
5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
Servers
Power monitoring and control/power budgeting
Telecommunication and data communication equipment
GENERAL DESCRIPTION
The ADM1278 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current, voltage, power, and temperature readback via an integrated
12-bit analog-to-digital converter (ADC), accessed using a PMBus™
interface. The load current is measured using an internal current
sense amplifier that measures the voltage across a sense resistor
in the power path via the HS+ and HS− pins. A default current
limit of 20 mV is set, but this limit can be adjusted, if required.
The ADM1278 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage, and therefore
the load current, is maintained below the preset maximum. The
ADM1278 protects the external FET by limiting the time that
the FET remains on while the current is at its maximum value.
This current-limit time is set by the choice of capacitor connected
to the TIMER pin. In addition, a constant power foldback scheme
is used to control the power dissipation in the MOSFET during
power-up and fault conditions. The level of this power, along
with the TIMER regulation time, can be set to ensure that the
MOSFET remains within safe operating area (SOA) limits.
TYPICAL APPLICATION CIRCUIT
4.5V TO 20V
RSENSE
Q1
HS+ MO+
MO– HS–
VCC
VCAP
UV
OV
ISET
PSET
ISTART
LDO
+×50–
ISENSE
ADM1278-1
CHARGE
PUMP
VCP
+
1.0V
GATE
DRIVE/
LOGIC
1.0V +
TIMEOUT
+
REF
+
SELECT
1.0V
CURRENT-
1.0V
HS–
LIMIT
CONTROL
GATE
TEMP
PWGIN
VOUT
VCBOS
TIMER
RETRY
IOUT
TIMER TIMEOUT
HS+
ISENSE
VOUT
TEMP
12-BIT
ADC
LOGIC
AND
PMBus
ANALOG
VOUT
PWRGD
FAULT
ENABLE
GPO2/ALERT2
GPO1/ALERT1/CONV
SCL
SDA
ADR1
ADR2
CSOUT
PGND GND
Figure 1.
In case of a short-circuit event, a fast internal overcurrent
detector responds within 320 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1278 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UV and OV pins. A PWRGD signal can be used to detect when
the output supply is valid, using the PWGIN pin to accurately
monitor the output.
The ADM1278 is available in a 32-lead LFCSP with a RETRY pin
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.
Table 1. Model Options
Model
ADC Accuracy
ADM1278-1AA ±0.3%
ADM1278-1A ±0.7%
ADM1278-1B ±1.0%
ADM1278-2A ±0.7%
ADM1278-3A ±0.7%
SPI Interface
No
No
No
Yes
No
Enable Pin1
Active high
Active high
Active high
Active high
Active low
1 Active high relates to the ENABLE pin, and active low relates to the ENABLE pin.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADM1278 Datasheet, Funktion
Data Sheet
ADM1278
Parameter1
Symbol
Min Typ Max Unit Test Conditions/Comments
HOT SWAP SENSE VOLTAGE
Hot Swap Sense Voltage
Current Limit
VSENSECL
A Grade and AA Grade
19.75 20 20.25 mV VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
B Grade Only
19.6 20 20.4 mV VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
Constant Power Inactive
VGATE = (VHS+ + 3 V); IGATE = 0 μA; VDS = (HS−) − VOUT
A Grade and AA Grade
24.75 25 25.25 mV VISET = 1.25 V; VDS < 2 V
19.75 20 20.25 mV VISET = 1.0 V; VDS < 2 V
14.75 15 15.25 mV VISET = 0.75 V; VDS < 2 V
B Grade Only
24.6 25 25.4 mV VISET = 1.25 V; VDS < 2 V
19.6 20 20.4 mV VISET = 1.0 V; VDS < 2 V
14.6 15 15.4 mV VISET = 0.75 V; VDS < 2V
Constant Power Active
FET power limit = (VPSET × 8)/(50 × RSENSE); constant power
active when VDS > (VPSET × 8)/ISET
A Grade and AA Grade
9.25 10 10.75 mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
4.65 5 5.35 mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 8 V
1.7
2 2.3
mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 20 V
B Grade Only
9
10 11
mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
4.6
5 5.4
mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 8 V
1.4
2 2.6
mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 20 V
Start-Up Current Limit
VISTARTCL
A Grade and AA Grade
4.7 5 5.3 mV STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
3.7
4 4.3
mV VISTART = 0.2 V
B Grade Only
4.5 5 5.5 mV STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
3.5
4 4.5
mV VISTART = 0.2 V
Start-Up Current-Limit Clamp VISTARTCL_CLAMP
A Grade and AA Grade
1.6 2 2.4 mV VISTART = 0 V or STRT_UP_IOUT_LIM = 0
B Grade Only
1.4 2 2.6 mV VISTART = 0 V or STRT_UP_IOUT_LIM = 0
Circuit Breaker Offset
VCBOS
0.6 0.88 1.12 mV Circuit breaker trip voltage, VCB = VSENSECL − VCBOS
SEVERE OVERCURRENT
Voltage Threshold
VSENSEOC
A Grade and AA Grade
23
25 27
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
28
30 32
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (150%)
38
40 42
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (200%)
43
45 47
mV VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
B Grade Only
20
25 30
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
25
30 35
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (150%)
35
40 45
mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (200%)
40
45 50
mV VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
Short Glitch Filter Duration
100
220 ns
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
Long Glitch Filter Duration
(Default)
530
900 ns
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
Response Time
Short Glitch Filter
200
320 ns
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
Long Glitch Filter
630
1000 ns
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
ISTART PIN
Active Range
0.1
1.25 V
Tie ISTART to VCAP to disable start-up current limit
Gain of Current Sense Amplifier AVCSAMP
50 V/V Accuracies included in total sense voltage accuracies
Input Current
IISTART
100 nA VISTART ≤ VVCAP
TIMER PIN
TIMER Pull-Up Current
Power-On Reset (POR)
ITIMERUPPOR
−2
−3 −4
µA Initial power-on reset; VTIMER = 0.5 V
Overcurrent (OC) Fault
ITIMERUPFLT
−57 −60 −63 µA Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V
Rev. A | Page 5 of 61

6 Page









ADM1278 pdf, datenblatt
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1278
PSET 1
VCAP 2
ISET 3
ISTART 4
TIMER 5
FAULT 6
ADR1 7
ADR2 8
ADM1278-1
TOP VIEW
(Not to Scale)
24 GATE
23 PGND
22 GND
21 PWGIN
20 VOUT
19 CSOUT
18 PWRGD
17 RETRY
PSET 1
VCAP 2
ISET 3
ISTART 4
TIMER 5
FAULT 6
ADR1 7
ADR2 8
ADM1278-3
TOP VIEW
(Not to Scale)
24 GATE
23 PGND
22 GND
21 PWGIN
20 VOUT
19 CSOUT
18 PWRGD
17 RETRY
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. SOLDER THE EXPOSED PAD TO THE BOARD
TO IMPROVE THERMAL DISSIPATION. THE EXPOSED
PAD CAN BE CONNECTED TO GROUND.
Figure 4. ADM1278-1 Pin Configuration
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. SOLDER THE EXPOSED PAD TO THE BOARD
TO IMPROVE THERMAL DISSIPATION. THE EXPOSED
PAD CAN BE CONNECTED TO GROUND.
Figure 5. ADM1278-3 Pin Configuration
Table 8. ADM1278-1 and ADM1278-3 Pin Function Descriptions
Mnemonic
Pin No. ADM1278-1 ADM1278-3 Description
1 PSET
PSET
Power Limit. This pin allows the constant power limit to be programmed. The current limit is
dynamically adjusted to ensure that the maximum power dissipation in the FET never
exceeds this limit during any operating condition. The power limit can be adjusted to a user
defined value using a resistor divider from VCAP. An external reference can also be used. The
FET power is limited to (VPSET × 8)/(50 × RSENSE).
2 VCAP
VCAP
Internal Regulated Supply. Place a capacitor with a value of 1 µF or greater on this pin to
maintain accuracy. This pin can be used as a reference to program the ISET pin voltage.
3 ISET ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit
is set when this pin is connected directly to VCAP. To achieve a user defined sense voltage,
the current limit can be adjusted using a resistor divider from VCAP. An external reference
can also be used.
4 ISTART
ISTART
Start-Up Current Limit. This pin allows a separate start-up current limit to be set for dv/dt
power-up mode. When powering up in dv/dt mode, the current charging the capacitor is
constant and is typically much smaller than the normal load current. The ISTART pin sets the
start-up current limit in a similar manner as ISET is used to set the normal current limit. The
start-up current limit is only active while PWRGD is low. The start-up current limit can also be
set over PMBus with the STRT_UP_IOUT_LIM register. Start-up current limit = VISET ×
(STRT_UP_IOUT_LIM/16). The lowest of all the active current limits always takes priority.
5 TIMER
TIMER
Timer. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The
GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold.
6 FAULT
FAULT
Fault. This pin asserts low and latches after a fault has occurred. The faults that can trigger
this pin include an overcurrent fault resulting in the TIMER pin voltage exceeding the upper
threshold, an overtemperature fault, and an FET health fault. This is an open-drain output
pin.
7, 8
ADR1, ADR2
ADR1, ADR2
PMBus Address. These pins can be tied to GND, tied to VCAP, left floating, or tied low through
a resistor for a total of 16 unique PMBus device addresses (see the Device Addressing
section).
9, 10, NIC NIC Not Internally Connected.
11
Rev. A | Page 11 of 61

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